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EVAL-ADE7880EBZ 数据表(PDF) 50 Page - Analog Devices

部件名 EVAL-ADE7880EBZ
功能描述  Polyphase Multifunction Energy Metering IC
PDF  104 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

EVAL-ADE7880EBZ 数据表(HTML) 50 Page - Analog Devices

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ADE7880
Data Sheet
Rev. A | Page 50 of 104
Fundamental Reactive Power Offset Calibration
Table 16 presents the settling time for the fundamental reactive
power measurement, which is the time it takes the power to
reflect the value at the input of the ADE7880.
The ADE7880 provides a fundamental reactive power offset
register on each phase. The AFVAROS, BFVAROS, and CFVAROS
registers compensate the offsets in the fundamental reactive
power calculations. These are signed twos complement, 24-bit
registers that are used to remove offsets in the fundamental
reactive power calculations. An offset can exist in the power
calculation due to crosstalk between channels on the PCB or in
the chip itself. The resolution of the registers is the same as for
the active power offset registers (see the Active Power Offset
Calibration section).
Table 16. Settling Time for Fundamental Reactive Power
Input Signals
63% PMAX
100% PMAX
375 ms
875 ms
Fundamental Reactive Power Gain Calibration
The average fundamental reactive power from the LPF output in
each phase can be scaled by ±100% by writing to one of the phase’s
VAR gain 24-bit register (APGAIN, BPGAIN, or CPGAIN). Note
that these registers are the same gain registers used to
compensate the other powers computed by the ADE7880. See
the Active Power Gain Calibration section for details on these
registers.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. Similar to the registers presented
in Figure 43, the AFVAROS, BFVAROS, and CFVAROS 24-bit
signed registers are accessed as 32-bit registers with the four
MSBs padded with 0s and sign extended to 28 bits.
INTERNAL
ACCUMULATOR
THRESHOLD
HPFEN BIT
CONFIG3[0]
HPF
DIGITAL SIGNAL PROCESSOR
AIGAIN
AVGAIN
HPFEN BIT
CONFIG3[0]
DIGITAL
INTEGRATOR
HPF
VA
IA
FUNDAMENTAL
REACTIVE
POWER
ALGORITHM
APGAIN
AFVAROS
APHCAL
24
AFVAR
:
VARTHR
34
27 26
0
0
32-BIT REGISTER
AFVARHR[31:0]
REVFRPA BIT IN
STATUS0[31:0]
Figure 77. Fundamental Reactive Energy Accumulation



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