EVAL-ADE7880EBZ datasheet(51/104 Pages) AD

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Data Sheet

ADE7880

Rev. A | Page 51 of 104

Sign of Fundamental Reactive Power Calculation

Note that the fundamental reactive power is a signed calculation.

Table 17 summarizes the relationship between the phase difference

between the voltage and the current and the sign of the resulting

reactive power calculation.

The ADE7880 has sign detection circuitry for reactive power

calculations that can monitor the fundamental reactive powers.

As described in the Fundamental Reactive Energy Calculation

section, the reactive energy accumulation is executed in two

stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the energy

accumulated into the internal accumulator reaches the VARTHR

each phase reactive power can be read in the PHSIGN register.

Bits[12:10] (REVFRPC, REVFRPB, and REVFRPA, respect-

tively) in the STATUS0 register are set when a sign change

occurs in the fundamental reactive power.

Bits[6:4] (CFVARSIGN, BFVARSIGN, and AFVARSIGN,

respectively) in the PHSIGN register are set simultaneously with

the REVFRPC, REVFRPB, and REVFRPA bits. They indicate the

sign of the fundamental reactive power. When they are 0, the

reactive power is positive. When they are 1, the reactive power

is negative.

Bit REVFRPx of the STATUS0 register and Bit xFVARSIGN in

the PHSIGN register refer to the reactive power of Phase x.

Setting Bits[12:10] in the MASK0 register enables the REVFRPC,

REVFRPB, and REVFRPA interrupts, respectively. If enabled,

the IRQ0 pin is set low and the status bit is set to 1 whenever a

change of sign occurs. To find the phase that triggered the

interrupt, the PHSIGN register is read immediately after read-

ing the STATUS0 register. Next, the status bit is cleared and the

IRQ0 pin is set to high by writing to the STATUS0 register with

the corresponding bit set to 1.

Table 17. Sign of Reactive Power Calculation

Φ1

Sign of Reactive Power

Between 0 to +180

Positive

Between −180 to 0

Negative

1 Φ is defined as the phase angle of the voltage signal minus the current

signal; that is, Φ is positive if the load is inductive and negative if the load is

capacitive.

Fundamental Reactive Energy Calculation

Fundamental reactive energy is defined as the integral of

fundamental reactive power.

Reactive Energy = ∫q(t)dt

(36)

The fundamental reactive energy accumulation is always a

signed operation. Negative energy is subtracted from the

reactive energy contents.

Similar to active power, the ADE7880 achieves the integration

of the reactive power signal in two stages (see Figure 77).

•

The first stage accumulates the instantaneous phase

fundamental reactive power at 1.024 MHz, although they

are computed by the DSP at 8 kHz rate. Every time a

threshold is reached, a pulse is generated and the threshold

is subtracted from the internal register. The sign of the

energy in this moment is considered the sign of the

reactive power (see the Sign of Fundamental Reactive

Power Calculation section for details).

•

The second stage consists in accumulating the pulses

generated after the first stage into internal 32-bit

accumulation registers. The content of these registers is

transferred to the var-hour registers (xFVARHR) when these

registers are accessed. AFWATTHR, BFWATTHR, and

CFWATTHR represent phase fundamental reactive energies.

Figure 77 explains this process. The threshold is formed by

concatenating the VARTHR 8-bit unsigned register to 27 bits

equal to 0 and it is introduced by the user. Its value depends on

how much energy is assigned to one LSB of var-hour registers.

Supposing a derivative of a volt ampere reactive hour (varh) [10n

varh] where n is an integer, is desired as one LSB of the VARHR

following equation:

3600

PMAX

VARTHR

(37)

where:

PMAX = 27,059,678 = 0x19CE5DE, the instantaneous power

computed when the ADC inputs are at full scale.

fS = 1.024 MHz, the frequency at which every instantaneous

power computed by the DSP at 8 kHz is accumulated.

UFS, IFS are the rms values of phase voltages and currents when

the ADC inputs are at full scale.

VARTHR register is an 8-bit unsigned number, so its maximum

value is 28 − 1. Its default value is 0x3. Values lower than 3, that

is 2 or 1 should be avoided and 0 should never be used as the

threshold must be a non-zero value.

This discrete time accumulation or summation is equivalent to

integration in continuous time, shown in Equation 38:

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

ergy

ReactiveEn

(38)

where:

n is the discrete time sample number.

T is the sample period.

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