ADL5363ACPZ-R7 datasheet(17/24 Pages) AD

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ADL5363

Rev. 0 | Page 17 of 24

CIRCUIT DESCRIPTION

RF SUBSYSTEM

The ADL5363 consists of two primary components: the radio

frequency (RF) subsystem and the local oscillator (LO) subsystem.

The combination of design, process, and packaging technology

allows the functions of these subsystems to be integrated

into a single die, using mature packaging and interconnection

technologies to provide a high performance, low cost design

with excellent electrical, mechanical, and thermal properties.

In addition, the need for external components is minimized,

optimizing cost and size.

The single-ended, 50 Ω RF input is internally transformed to a

balanced signal using a low loss (<1 dB) unbalanced-to-balanced

(balun) transformer. This transformer is made possible by an

extremely low loss metal stack, which provides both excellent

balance and dc isolation for the RF port. Although the port can

be dc connected, it is recommended that a blocking capacitor be

used to avoid running excessive dc current through the part.

The RF balun can easily support an RF input frequency range

of 2300 MHz to 2900 MHz.

The RF subsystem consists of an integrated, low loss RF balun,

passive MOSFET mixer, sum termination network.

The resulting balanced RF signal is applied to a passive mixer

that commutates the RF input with the output of the LO subsystem.

The passive mixer is essentially a balanced, low loss switch that

adds minimum noise to the frequency translation. The only

noise contribution from the mixer is due to the resistive loss

of the switches, which is in the order of a few ohms.

The LO subsystem consists of an SPDT-terminated FET switch

and a three-stage limiting LO amplifier. The purpose of the LO

subsystem is to provide a large, fixed amplitude, balanced signal

to drive the mixer independent of the level of the LO input.

A block diagram of the device is shown in Figure 48.

As the mixer is inherently broadband and bidirectional, it

is necessary to properly terminate all the idler (M × N product)

frequencies generated by the mixing process. Terminating the

mixer avoids the generation of unwanted intermodulation

products and reduces the level of unwanted signals at the IF

output. This termination is accomplished by the addition of a

sum network between the IF output and the mixer.

BIAS

GENERATOR

VPMX

RFIN

RFCT

COMM

LOI2

VPSW

VGS1

VGS0

LOI1

VCMI

IFOP

IFON

PWDN

COMM

VLO3

LGM3

VLO2

LOSW

ADL5363

NC = NO CONNECT

The IP3 performance can be optimized by adjusting the supply

current with an external resistor. Figure 37 and 38 illustrate how

the bias resistor affects the performance with a 5 V supply.

Additionally, dc current can be saved by increasing either or

both resistors. It is permissible to reduce the dc supply voltage

to as low as 3.3 V, further reducing the dissipated power of the

part. (Note that no performance enhancement is obtained by

reducing the value of these resistors and excessive dc power

dissipation may result.)

Figure 48. Simplified Schematic

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