ADRF6516ACPZ-R7 datasheet(18/32 Pages) AD

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ADRF6516

Data Sheet

Rev. B | Page 18 of 32

GAIN

FROM

FILTERS

COFS

OFSx

OFDS

50dB

VGA

OUTPUT ADC

DRIVER

BASEBAND

OUTPUTS

Figure 48. Offset Compensation Loop Operates Around the VGA

and Output Buffer

The offset compensation loop creates a high-pass corner, fHP,

that is superimposed on the normal Butterworth filter response.

Typically, fHP is many orders of magnitude lower than the lowest

programmed filter bandwidth so that there is no interaction

between them. Setting fHP is accomplished with capacitors,

COFS, from the OFS1 and OFS2 pins to ground. Because the

compensation loop works around the VGA sections, fHP is also

dependent on the total gain of the cascaded VGAs. In general,

the expression for fHP is given by

fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF))

where Post Filter Linear Gain is expressed in linear terms, not

in decibels (dB), and is the gain following the filters, which

excludes the preamplifier gain of 1.4 (3 dB) or 2 (6 dB).

Note that fHP increases in proportion to the gain. For this reason,

COFS should be chosen at the highest operating gain to guarantee

that fHP is always below the maximum limit required by the system.

PROGRAMMING THE FILTERS AND GAINS

The 0.5 dB corner frequencies for both filters and the gains of

the preamplifiers and postamplifiers are programmed simulta-

neously through the SPI port. An 8-bit register stores the 5-bit

code for corner frequencies of 1 MHz through 31 MHz, as well

as the 1-bit codes for the preamplifier gain, the VGA maximum

gain, and the postamplifier gain (see Table 4). The SPI protocol

not only allows frequency and gain codes to be written to the

DATA pin, but it also allows the stored code to be read back via

the SDO pin.

The latch enable (LE) pin must first go to a Logic 0 for a read or

write cycle to begin. On the next rising edge of the clock (CLK),

a Logic 1 on the DATA pin initiates a write cycle, whereas a

Logic 0 on the DATA pin initiates a read cycle. In a write cycle,

the next eight CLK rising edges latch the desired 8-bit code, LSB

first. When LE goes high, the write cycle is completed and the

frequency and gain codes are presented to the filter and ampli-

fiers. In a read cycle, the next eight CLK falling edges present

the stored 8-bit code, LSB first. When LE goes high, the read

cycle is completed. Detailed timing diagrams are shown in

Figure 2 and Figure 3.

NOISE CHARACTERISTICS

The output noise behavior of the ADRF6516 depends on the gain

and bandwidth settings. Figure 49 and Figure 50 show the total

output noise spectral density vs. frequency for different band-

width settings and VGA gains.

–150

–145

–140

–135

–130

–125

–120

–115

–110

FREQUENCY (MHz)

BANDWIDTH = 31MHz

DIGITAL GAIN = 111

GAIN = 20dB

GAIN = 0dB

GAIN = 40dB

Figure 49. Total Output Noise Density with a 31 MHz Corner Frequency

for Three Different Gain Settings

–150

–145

–140

–135

–130

–125

–120

–115

–110

–105

–100

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2

FREQUENCY (MHz)

GAIN = 20dB

GAIN = 0dB

GAIN = 40dB

BANDWIDTH = 1MHz

DIGITAL GAIN = 111

Figure 50. Total Output Noise Density with a 1 MHz Corner Frequency

for Three Different Gain Settings

Both the filter sections and the VGAs contribute to the total noise

at the output. The filter contributes a noise spectral density profile

that is flat at low frequencies, peaks near the corner frequency, and

then rolls off as the filter poles roll off the gain and noise. The

magnitude of the noise spectral density contributed by the filter,

expressed in nV/√Hz, varies inversely with the square root of the

bandwidth setting, resulting in a total integrated noise in nV that is

nearly constant with bandwidth setting. At higher frequencies,

after the filter noise rolls off, the noise floor is set by the VGAs.

Each of the X-AMP VGA sections used in the ADRF6516 con-

tributes a fixed and flat noise spectral density to its respective

output, independent of the gain setting. Because the VGAs are

cascaded in the ADRF6516, the total noise contributed by the

VGAs at the output increases gradually with higher gain. This

is apparent in the noise floor variation at high frequencies at

different VGA gain settings.

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