ADRF6516ACPZ-R7 datasheet(21/32 Pages) AD

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Data Sheet

ADRF6516

Rev. B | Page 21 of 32

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 51 shows the basic connections for a typical ADRF6516

application.

SUPPLY DECOUPLING

A nominal supply voltage of 3.3 V should be applied to the

supply pins. The supply voltage should not exceed 3.45 V

or drop below 3.15 V. Each supply pin should be decoupled

to ground with at least one low inductance, surface-mount

ceramic capacitor of 0.1 µF placed as close as possible to the

ADRF6516 device.

The ADRF6516 has two separate supplies: an analog supply and

a digital supply. Care should be taken to separate the analog and

digital supplies with a large surface-mount inductor of 33 µH.

Each supply should then be decoupled separately to its respective

ground through a 10 μF capacitor.

INPUT SIGNAL PATH

Each signal path has input buffers, accessed through the

INP1, INM1, INP2, and INM2 pins, that set a differential input

impedance of 1600 Ω. These inputs sit at a nominal common-

mode voltage around midsupply.

The inputs can be dc-coupled or ac-coupled. If using direct

dc coupling, the common-mode voltage, VCM, can range from

1.1 V to 1.8 V. The VICM pin can be used as a reference common-

mode voltage for driving a high impedance sensing node of the

preceding cascaded part (VICM has a 7 kΩ impedance).

For example, the high impedance VOCM input pin of the

ADRF6806 quadrature demodulator can be directly connected

to the VICM pin of the ADRF6516. This gives the ADRF6806

the optimal common-mode voltage reference to drive the

ADRF6516.

OUTPUT SIGNAL PATH

The low impedance (30 Ω) output buffers are designed to drive

a high impedance load, such as an ADC input or another amplifier

stage. The output pins—OPP1, OPM1, OPP2, and OPM2—sit

at a nominal output common-mode voltage of VPS/2, but can

be driven to a voltage of 0.7 V to 2.8 V by applying the desired

common-mode voltage to the high impedance VOCM pin.

DC OFFSET COMPENSATION LOOP ENABLED

When the dc offset compensation loop is enabled via the OFDS

pin, the ADRF6516 can null the output differential dc level. The

loop is enabled by pulling the OFDS pin low to ground. The

offset compensation loop creates a high-pass corner frequency,

which is proportional to the value of the capacitors that are

connected from the OFS1 and OFS2 pins to ground. For more

information about setting the high-pass corner frequency, see

the DC Offset Compensation Loop section.

COMMON-MODE BYPASSING

The ADRF6516 common-mode pins, VICM and VOCM, must

be decoupled to ground. At least one low inductance, surface-

mount ceramic capacitor with a value of 0.1 μF should be used

to decouple the common-mode pins.

VPSD

COMD

CLK

DATA

SDO

COM

VPS

OPP1

OPM1

COM

GAIN

VOCM

COM

OPM2

OPP2

COM

INP2

INM2

VPS

COM

OFDS

OFS2

VPS

ENBL

INP1

INM1

VPS

COM

VICM

OFS1

VPS

ADRF6516

VPS

VPSD

0.1µF

VPS

OUTPUT1 (+)

INPUT1 (–)

0.1µF

INPUT1 (+)

INPUT2 (+)

INPUT2 (–)

OUTPUT1 (–)

OUTPUT2 (–)

OUTPUT2 (+)

0.1µF

SERIAL

CONTROL

INTERFACE

VPS

0.1µF

Figure 51. Basic Connections

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