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ADRF6701ACPZ-R7 数据表(PDF) 27 Page - Analog Devices |
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ADRF6701ACPZ-R7 数据表(HTML) 27 Page - Analog Devices |
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27 / 36 page ![]() Data Sheet ADRF6701 Rev. 0 | Page 27 of 36 REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0X1E2106) With Register 6, Bits[2:0] set to 110, the VCO control and enable register is programmed as shown in Figure 47. The VCO tuning band is normally selected automatically by the band calibration algorithm, although the user can directly select the VCO band using Register 6. The VCO BSSRC bit (DB9) determines whether the result of the calibration algorithm is used to select the VCO band or if the band selected is based on the value in VCO band select (DB8 to DB3). The VCO amplitude can be controlled through Register 6. The VCO amplitude setting can be controlled between 0 and 63. The default value of 8 should be set to a recommended value of 63. The internal VCOs can be disabled using Register 6. The internal charge pump can be disabled through Register 6. By default, the charge pump is enabled. To turn off the PLL (for example, if the ADRF6701 is being driven by an external LO), set Register 6, Bits[20:17] to zero. REGISTER 7—EXTERNAL VCO ENABLE AND SECOND LO DIVIDER With Register 7, Bits[2:0] set to 111, the external VCO control register is programmed as shown in Figure 48. The external VCO enable bit allows the use of an external VCO in the PLL instead of the internal VCO. This can be advantageous in cases where the internal VCO is not capable of providing the desired frequency or where the internal VCO’s phase noise is higher than desired. By setting this bit (DB22) to 1, and setting Register 6, Bits[15:10] to 0, the internal VCO is disabled, and the output of an external VCO can be fed into the part differ- entially on Pin 38 and Pin 37 (LOP and LON). Because the loop filter is already external, the output of the loop filter simply needs to be connected to the external VCO’s tuning voltage pin. In addition, Register 7 provides control over a divide-by-2 block in the LO path using Bit DB4. If DB4 is set to 1, then the divide- by-2 block is bypassed, and an external 2× LO can be used to drive the modulator. CHARGE PUMP ENABLE 3.3V LDO ENABLE VCO ENABLE VCO SWITCH VCO BW SW CTRL VBSRC 0 1 VCO EN VCO LDO ENABLE VCO AMPLITUDE RESERVED VCO BAND SELECT FROM SPI VBS[5:0] VCO BAND SELECT FROM SPI 0x00 DEFAULT 0x20 CHARGE PUMP ENABLE 0x01 …. 0x00 0 …. …. 0x08 8 (DEFAULT) …. …. 0x2B 43 …. …. 0x3F 63 (RECOMMENDED) 0x3F VCO BW CAL AND SW SOURCE CONTROL BAND CAL (DEFAULT) VCO SW 0 1 VCO SWITCH CONTROL FROM SPI REGULAR (DEFAULT) BAND CAL SPI VCO ENABLE DISABLE ENABLE (DEFAULT) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS DB23 CPEN L3EN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0) LVEN VC[5:0] VCO AMPLITUDE 0 1 LVEN VCO LDO ENABLE DISABLE ENABLE (DEFAULT) 0 1 L3EN 3.3V LDO ENABLE DISABLE ENABLE (DEFAULT) 0 1 CPEN DISABLE ENABLE (DEFAULT) 0 1 00 0 Figure 47. Register 6—VCO Control and VCO Enable Register Map DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 XVCO EXTERNAL VCO ENABLE RES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(1) C1(1) RESERVED CONTROL BITS XVCO 0 1 INTERNAL VCO (DEFAULT) EXTERNAL VCO EXTERNAL VCO ENABLE LDIV2 0 1 DIVIDE BY 4 (DEFAULT) LO PATH DIVIDE RATIO DIVIDE BY 2 Figure 48. Register 7—External VCO Enable Register Map |
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