ADRF6701ACPZ-R7 datasheet(16/36 Pages) AD

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ADRF6701

Data Sheet

Rev. 0 | Page 16 of 36

THEORY OF OPERATION

The ADRF6701 integrates a high performance IQ modulator

with a state of the art fractional-N PLL. The ADRF6701 also

integrates a low noise VCO. The programmable SPI port allows

the user to control the fractional-N PLL functions and the

modulator optimization functions. This includes the capability

to operate with an externally applied LO or VCO.

The quadrature modulator core within the ADRF6701 is a part

of the next generation of industry-leading modulators from

Analog Devices, Inc. The baseband inputs are converted to

currents and then mixed to RF using high performance NPN

transistors. The mixer output currents are transformed to a

single-ended RF output using an integrated RF transformer

balun. The high performance active mixer core, coupled with

the low-loss RF transformer balun results in an exceptional

OIP3 and OP1dB, with a very low output noise floor for excel-

lent dynamic range. The use of a passive transformer balun

rather than an active output stage leads to an improvement

in OIP3 with no sacrifice in noise floor. At 950 MHz, the

ADRF6701 typically provides an output P1dB of 10 dBm, OIP3

of 32 dBm, and an output noise floor of −157.8 dBm/Hz. Typical

image rejection under these conditions is −44 dBc with no

additional I and Q gain compensation.

PLL + VCO

The fractional divide function of the PLL allows the frequency

multiplication value from REFIN to the LOP/LON outputs to

be a fractional value rather than restricted to an integer as in

traditional PLLs. In operation, this multiplication value is INT

+ (FRAC/MOD) where INT is the integer value, FRAC is the

fractional value, and MOD is the modulus value, all of which

are programmable via the SPI port. In previous fractional-N

PLL designs, the fractional multiplication was achieved by

periodically changing the fractional value in a deterministic

way. The downside of this was often spurious components close

to the fundamental signal. In the ADRF6701, a sigma delta

modulator is used to distribute the fractional value randomly,

thus significantly reducing the spurious content due to the

fractional function.

BASIC CONNECTIONS FOR OPERATION

Figure 35 shows the basic connections for operating the

ADRF6701 as they are implemented on the device’s evaluation

board. The seven power supply pins should be individually

decoupled using 100 pF and 0.1 μF capacitors located as close

as possible to the pins. A single 10 μF capacitor is also recom-

mended. The three internal decoupling nodes (labeled DECL3,

DECL2, and DECL1) should be individually decoupled with

capacitors as shown in Figure 35.

The four I and Q inputs should be driven with a bias level of

500 mV. These inputs are generally dc-coupled to the outputs of

a dual DAC (see the DAC-to-IQ Modulator Interfacing and IQ

Filtering sections for more information).

A 1 V p-p (0.353 V rms) differential sine wave on the I and Q

inputs results in a single sideband output power of +4.1 dBm (at

950 MHz) at the RFOUT pin (this pin should be ac-coupled as

shown in Figure 35). This corresponds to an IQ modulator

voltage gain of −0.2 dB.

The reference frequency for the PLL (typically 1 V p-p between

12 MHz and 160 MHz) should be applied to the REFIN pin,

which should be ac-coupled. If the REFIN pin is being driven

from a 50 Ω source (for example, a lab signal generator), the

pin should be terminated with 50 Ω as shown in Figure 35 (an

RF drive level of +4 dBm should be applied). Multiples or

fractions of the REFIN signal can be brought back off-chip at

the multiplexer output pin (MUXOUT). A lock-detect signal

and an analog voltage proportional to the ambient temperature

can also be brought out on this pin by setting the appropriate

bits on (DB21-DB23) in Register 4 (see the Register Description

section).

EXTERNAL LO

The internally generated local oscillator (LO) signal can be

brought off-chip as either a 1× LO or a 2× LO or a 4× LO (via

the LOP and LON pins) by asserting the LOSEL pin and

making the appropriate internal register settings. The LO

output must be disabled whenever the RF output of the IQ

modulator is disabled.

The LOP and LON pins can also be used to apply an external

LO. This can be used to bypass the internal PLL/VCO or if

operation using an external VCO is desired. To turn off the

PLL Register 6, Bits[20:17] must be zero.

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