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ADP2381AREZ-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADP2381AREZ-R7
功能描述  20 V, 6 A Synchronous Step-Down
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2381AREZ-R7 数据表(HTML) 18 Page - Analog Devices

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ADP2381
Data Sheet
Rev. 0 | Page 18 of 28
PROGRAMMING INPUT VOLTAGE UVLO
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling
threshold of PVIN and UVLO are listed in Table 9. These
default values can be replaced by using an external voltage
divider to achieve a more accurate externally adjustable UVLO,
as shown in Figure 32. Lower values of the external resistors are
recommended to obtain a high accuracy UVLO threshold
because the values of the internal 320 kΩ and 125 kΩ resistors
may vary by as much as 20%.
Table 9. Default Rising/Falling Voltage Threshold
Pin
Rising Threshold (V)
Falling Threshold (V)
PVIN
4.28
3.92
UVLO
1.2
1.1
Figure 32. External Programmable UVLO
A 1 kΩ resistor for R2 is an appropriate choice. Use the
following equation to obtain the value of R1 for a chosen input
voltage rising threshold:
(
)
V
2
.
1
V
2
.
1
_
R2
V
R1
RISING
IN
×
−
=
where VIN_RISING is the rising threshold of VIN.
The falling threshold of VIN can be determined by the
following equation:
V
1
.
1
2
V
1
.
1
_
+
×
=
R
R1
V FALLING
IN
where VIN_FALLING is the falling threshold of VIN.
COMPENSATION DESIGN
The ADP2381 uses a peak current-mode control architecture
for excellent load and line transient response. For peak current-
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
The control to output transfer function is given by the following
equation:
P
Z
VI
COMP
OUT
VD
f
s
f
s
R
A
s
V
s
V
s
G
×
×
+
×
×
+
×
×
=
=
π
π
2
1
2
1
)
(
)
(
)
(
OUT
ESR
Z
C
R
f
×
×
×
=
π
2
1
OUT
ESR
P
C
R
R
f
×
+
×
×
=
)
(
2
1
π
where:
AVI = 8.7 A/V.
R is the load resistance.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
The external voltage loop is compensated by a transconduct-
ance amplifier with a simple external RC network placed either
between COMP and GND or between COMP and FB, as shown
in Figure 33 and Figure 34, respectively.
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control small
signal circuit with a compensation network placed between
COMP and GND.
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
The RC and CC compensation components contribute a zero,
and the optional CCP and RC contribute an optional pole.
The closed-loop transfer function is as follows:
)
(
1
1
)
(
s
G
s
C
C
C
C
R
s
s
C
R
C
C
g
R
R
R
s
T
VD
CP
C
CP
C
C
C
C
CP
C
m
TOP
BOT
BOT
V
×
×
+
×
×
+
×
×
×
+
×
+
−
×
+
=
Use the following design guidelines to select the RC, CC, and CCP
compensation components:
•
Determine the cross frequency, fC. Generally, fc is between
fSW/12 and fSW/6.
•
RC can be calculated by
VI
m
REF
C
OUT
OUT
C
A
g
V
f
C
V
R
×
×
×
×
×
×
=
π
2
where:
VREF = 0.6 V.
gm = 500 µS.
•
Place the compensation zero at the domain pole, fP. CC can
be determined by:
C
OUT
ESR
C
R
C
R
R
C
×
+
=
)
(
PVIN
VIN
R1
R2
UVLO
320kΩ
125kΩ
ADP2381
RESR
R
+
–
g
m
RC
CCP
COUT
CC
RTOP
RBOT
–
+
AVI
VOUT
VCOMP
VOUT
ADP2381
GND
COMP
FB



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