Sensor

26

Freescale Semiconductor, Inc.

MMA65xx

3.8.1

DSP Clock

The DSP is clocked at 8 MHz, with an effective 6MHz operating frequency. The clock to the DSP is disabled for 1 clock prior

to each edge of the

ΣΔ modulator clock to minimize noise during data conversion.

Figure 13. Clock Generation

3.8.2

Decimation Sinc Filter

The serial data stream produced by the

ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc

filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected.

3.8.3

Low Pass Filter

Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter.

.

The device provides the option for one of twelve low-pass filters. The filter is selected independently for each axis with the

LPF_X[3:0] and LPF_Y[3:0] bits in the DEVCFG_X and DEVCFG_Y registers. The filter selection options are listed in

Section 3.1.7.3, Table 11. Response parameters for the low-pass filter are specified in Section 2.4. Filter characteristics are illus-

trated in the figures on the following pages.

8 MHz OSC

6 MHz Digital

1MHz Modulator

Hz

()

1

z 16

–

–

16

1

z 1

–

–

()

×

-----------------------------------

3

=

Hz

()

n

0

n

1

z 1

–

⋅

()

n

2

z 2

–

⋅

()

n

3

z 3

–

⋅

()

n

4

z 4

–

⋅

()

++++

d

0

d

1

z 1

–

⋅

()

d

2

z 2

–

⋅

()

d

3

z 3

–

⋅

()

d

4

z 4

–

⋅

()

++++

---------------------------------------------------------------------------------------------------------------------------------

=