Sensor

36

Freescale Semiconductor, Inc.

MMA65xx

The effect of this interpolation at the system level is a 50% reduction in sample jitter. Figure 24 shows the resulting output data

for an input signal.

Figure 24. Data Interpolation Example

3.8.9

Acceleration Data Timing

The SPI uses a request/response protocol, where a SPI transfer is completed through a sequence of 2 phases. Reference

Section 4 for more details regarding the SPI protocol. The device latches the associated data for an acceleration request at the

rising edge of CS. The most recent sample available from the DSP (including interpolation) is latched, and transmitted during the

subsequent SPI transfer.

Figure 25. Acceleration Data Timing

40

45

50

55

60

65

70

75

80

0

5

10

15

20

25

30

35

40

Time

Input Signal

Internally Sampled Signal

Interpolated Samples

Internally

Sampled Values

Earliest Transmission

Point of Interpolated

Values

Earliest Transmission

Point of Internally

Sampled Values

Window of

Transmission for

Sampled Values

Window of

Transmission for

Interpolated Values

Fixed Latency:

= Signal Jitter =

SCLK

MOSI

MISO

CS

Request X-Axis

Request Y-Axis

X-Axis Response

Y-Axis Response

Request X-Axis

Request Y-Axis

X-Axis Response

X-Axis Data Latched

Y-Axis Data Latched

X-Axis Arm Function updated

Y-Axis Arm Function updated if applicable