M200/M500

Document Number: 001-29139 Rev. *C

Page 5 of 17

General Description

2 Configurable PLLs

clock generator ICs designed for cell phone, portable, or

consumer electronics applications. It can be used to generate

two independent output frequencies ranging from 3 to 50 MHz

from a single input reference clock.

that programs the configuration memory array to synthesize

output frequencies by programmable output divider, spread

in-system control of these programmable features.

Input Reference Clocks

The input to the M200 and M500 are designed to use an external

reference clock with a frequency range of 1 MHz to 48 MHz at

the EXCLKIN pin. The voltage level for the input reference clock

used must follow VDD voltage used for the device as shown in

the DC and AC specifications.

Output Power Supply Options

There are three clock outputs CLK1, CLK2, and CLK3 driven by

three separate output power supplies: VDD_CLK1, VDD_CLK2,

and VDD_CLK3 respectively. Different voltage level for each of

these power supplies can be used and they can be any of 1.5 V,

1.8 V, 2.5 V, 3.0 V, or 3.3 V giving user multiple choice of output

clock voltage levels.

Output Source Selection

These devices have three clock outputs, CLK1, CLK2 and CLK3.

There are three available clock sources for these outputs. These

clock sources are: PLL1, PLL2, or EXCLKIN. Output clock

source selection is done using three out of three crossbar switch.

Thus, any one of these three available clock sources can be

arbitrarily selected for the clock outputs. This gives user a

flexibility to have up to two independent clocks and a reference

clock output.

Spread Spectrum Control

The PLL2 has spread spectrum capability for EMI reduction in

the system. The device uses a Cypress proprietary PLL and

Spread Spectrum Clock (SSC) technology to synthesize and

modulate the frequency of the PLL. The spread spectrum feature

factory programmed to either center spread range from ±0.125%

to ±2.50%, or down spread range from –0.25% to –5.0%, with

Lexmark or Linear modulation profile.

PD#/OE Mode

PD#/OE input (Pin 4) can be programmed to operate as either

power down (PD#) or output enable (OE) mode. Note that power

down shuts off the entire chip, resulting in minimum power

consumption for the device. Setting this signal high brings the

device in the operational mode with default register settings. The

PD# turn-on time is limited by the turn-on time of the PLLs.

Disabled outputs are first driven to a low state before turning off.

When off, they are held low by internal weak resistors

(~160 kohms)

When this pin is programmed as Output Enable (OE), clock

outputs can be enabled or disabled using OE (pin 4). Individual

clock outputs can be programmed to be sensitive to this OE pin.

Keep Alive Mode

By activating the device in the Keep Alive Mode, power down

mode is changed to power saving mode, which disables all PLLs

and outputs, but preserves the contents of the volatile registers.

not preserved during power down, but power consumption is

reduced relative to the Keep Alive Mode.

Output Drive Strength

The DC drive strength of the individual clock output can be

programmed for different values. Table 3 shows the typical rise

and fall times for different drive strength settings.

Generic Configuration and Custom Frequency

The device is available with Factory Specific programmed

frequencies as shown in the Ordering Information page. This

factory specific programmed part can be used for the device

programmed to any desired frequencies and listed features. For

bitmap definitions, please contact local Cypress Field

Application Engineer (FAE) or sales representative.

Table 3. Output Drive Strength

Output Drive Strength

Rise/Fall Time (ns)

(Typical Value)

Low

6.8

Mid Low

3.4

Mid High

2.0

High

1.0

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