AFE5808A datasheet(33/66 Pages) TI1

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AFE5808A

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SLOS729B – OCTOBER 2011 – REVISED APRIL 2012

Table 4. VCA Register Map (continued)

ADDRESS

Default

FUNCTION

DESCRIPTION

(DEC)

(HEX)

Value

53[11]

0x35[11]

MED_POWER

0: Low noise mode;

1: Sets to medium power mode(53[10]=0). At 30dB PGA, total chain

gain may slightly change.

See typical characteristics

53[12]

0x35[12]

PDN_VCAT_PGA

0: Normal operation;

1: Powers down VCAT (voltage-controlled-attenuator) and PGA

53[13]

0x35[13]

PDN_LNA

0: Normal operation;

1: Powers down LNA only

53[14]

0x35[14]

VCA_PARTIAL_PDN

0: Normal operation;

1: Powers down LNA, VCAT, and PGA partially(fast wake response)

53[15]

0x35[15]

VCA_COMPLETE_PDN

0: Normal operation;

1: Powers down LNA, VCAT, and PGA completely (slow wake

response). This bit can overwrite 53[14].

54[4:0]

0x36[4:0]

CW_SUM_AMP_GAIN_CNTL

Selects Feedback resistor for the CW Amplifier as per Table 6 below

54[5]

0x36[5]

CW_16X_CLK_SEL

0: Accepts differential clock;

1: Accepts CMOS clock

54[6]

0x36[6]

CW_1X_CLK_SEL

0: Accepts CMOS clock;

1: Accepts differential clock

54[7]

0x36[7]

RESERVED

Set to 0

54[8]

0x36[8]

CW_TGC_SEL

0: TGC Mode;

1 : CW Mode

Note : VCAT and PGA are still working in CW mode. They should be

powered down separately through 53[12]

54[9]

0x36[9]

CW_SUM_AMP_ENABLE

0: enables CW summing amplifier;

1: disables CW summing amplifier

Note: 54[9] is only effective in CW mode.

54[11:10]

0x36[11:10]

CW_CLK_MODE_SEL

00: 16X mode;

01: 8X mode;

10: 4X mode;

11: 1X mode

55[3:0]

0x37[3:0]

CH1_CW_MIXER_PHASE

55[7:4]

0x37[7:4]

CH2_CW_MIXER_PHASE

55[11:8]

0x37[11:8]

CH3_CW_MIXER_PHASE

55[15:12]

0x37[15:12]

CH4_CW_MIXER_PHASE

0000

→1111, 16 different phase delays, see Table 9

56[3:0]

0x38[3:0]

CH5_CW_MIXER_PHASE

56[7:4]

0x38[7:4]

CH6_CW_MIXER_PHASE

56[11:8]

0x38[11:8]

CH7_CW_MIXER_PHASE

56[15:12]

0x38[15:12]

CH8_CW_MIXER_PHASE

57[1:0]

0x39[1:0]

CH1_LNA_GAIN_CNTL

00: 18dB;

01: 24dB;

57[3:2]

0x39[3:2]

10: 12dB;

CH2_LNA_GAIN_CNTL

11: Reserved

REG52[15] should be set as '1'

57[5:4]

0x39[5:4]

CH3_LNA_GAIN_CNTL

00: 18dB;

01: 24dB;

57[7:6]

0x39[7:6]

CH4_LNA_GAIN_CNTL

10: 12dB;

11: Reserved

57[9:8]

0x39[9:8]

CH5_LNA_GAIN_CNTL

REG52[15] should be set as '1'

57[11:10]

0x39[11:10]

CH6_LNA_GAIN_CNTL

57[13:12]

0x39[13:12]

CH7_LNA_GAIN_CNTL

57[15:14]

0x39[15:14]

CH8_LNA_GAIN_CNTL

59[3:2]

0x3B[3:2]

HPF_LNA

00: 100kHz;

01: 50kHz;

10: 200kHz;

11: 150kHz with 0.015uF on INMx

59[6:4]

0x3B[6:4]

DIG_TGC_ATT_GAIN

000: 0dB attenuation;

001: 6dB attenuation;

N: ~N×6dB attenuation when 59[7] = 1

59[7]

0x3B[7]

DIG_TGC_ATT

0: disable digital TGC attenuator;

1: enable digital TGC attenuator

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