TNETX4080 datasheet(32/64 Pages) TI1

32 / 64 page

TNETX4080

ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

EEPROM interface (continued)

After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then

EDIO is observed for an acknowledge from the EEPROM. If an acknowledge is received, operation continues

for the 24C02 EEPROM. If none is received, a stop condition is generated, followed by another start condition

and slave address, this time containing a device address of 100. If this receives no acknowledge, no EEPROM

is present, and device operation continues, using the current register settings (i.e., those following a hardware

reset, or those previously entered by software).

When this device is driving EDIO, it drives out only a strong logical 0. When a logical 1 is intended to be driven

out, the pin must be resistively pulled high. An on-chip 50-

µA current-source pullup device is provided on this

pin. The system designer must decide if this is sufficient to achieve a logical-1 level in a timely manner or if an

external supplementary resistor is required.

Multiple bus masters are not supported on the EEPROM interface because the ECLK pin always is driven by

the device with a strong 0/strong 1 (i.e., not a strong 1/resistively pulled-up 1).

An Ethernet CRC check is used to ensure the EEPROM data is valid. The 4-byte CRC should be placed within

the EEPROM in four data bytes immediately following the last byte to be loaded (equivalent to locations

0x00FC–0x00FF, just above SysControl). As each byte is loaded from the EEPROM, the bits within that byte

are entered into the CRC checker bit-wise, most significant bit first.

A valid CRC always must be provided by the EEPROM. The EEPROM data for the most significant bit of

SysControl is withheld until the CRC computed by the device has been checked against the one read from the

EEPROM. If the CRC is invalid:

D The reset bit is set to 1 in SysControl, load and initd are both 0, and the TNETX4080 does not begin

operation.

D The fault LED is illuminated and remains in that state until the TNETX4080 is hardware reset or until load

in SysControl is set to 1.

interaction of EEPROM load with the SIO register

The EDIO pin is shared with the SIO register edata bit. The edata and etxen bits must not both be set to 1 when

the load bit is set or the EDIO pin is held at resistive 1 and the EEPROM load fails.

The value of the eclk bit in SIO is don’t care when load is set, but to ensure the EEPROM does not see a glitch

on its clock signal, the load bit should not be set until the minimum clock high or low time required by the

EEPROM on its clock signal has expired since the eclk bit was last changed.

The SIO register is not loaded during the EEPROM download.

summary of EEPROM load outcomes

Table 8 summarizes the various states of register bits and the fault LED for each possible outcome following

an EEPROM load attempt.

Table 8. Summary of EEPROM Load Outcomes

OUTCOME

STOP

LOAD

INITD†

FAULT LED

ECLK

Successful load

0‡

Not locked

No EEPROM present

0‡

Locked

CRC error detected

Not locked

† Assuming the start bit was set to 1 by the EEPROM load

‡ Assuming the fault bit in LEDControl = 0 and no memory system parity error is detected

TNETX4080 数据表(PDF) 32 Page - Texas Instruments

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