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TNETX4080 数据表(PDF) 9 Page - Texas Instruments |
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TNETX4080 数据表(HTML) 9 Page - Texas Instruments |
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9 / 64 page  TNETX4080 ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M00_TXD3 M00_TXD2 M00_TXD1 M00_TXD0 M01_TXD3 M01_TXD2 M01_TXD1 M01_TXD0 M02_TXD3 M02_TXD2 M02_TXD1 M02_TXD0 M03_TXD3 M03_TXD2 M03_TXD1 M03_TXD0 M04_TXD3 M04_TXD2 M04_TXD1 M04_TXD0 M05_TXD3 M05_TXD2 M05_TXD1 M05_TXD0 M06_TXD3 M06_TXD2 M06_TXD1 M06_TXD0 M07_TXD3 M07_TXD2 M07_TXD1 M07_TXD0 C22 B22 A22 A23 C18 B18 A18 A19 D12 C12 B12 A12 D7 C7 B7 A7 G4 G3 G2 G1 M4 M3 M2 M1 U4 U3 U2 U1 AC5 AD5 AE5 AF5 O None Transmit data. Byte transmit data. When Mxx_TXEN is asserted, these signals carry transmit data. Data on these signals is synchronous to Mxx_RFCLK. When Mxx_TXEN, Mxx_TXER, and Mxx_LINK are all low, these pins indicate the desired capabilities for autonegotiation as follows: – Mxx_TXD0 indicates full-duplex capability when high; half duplex when low, as determined by reqhd in PortxControl. – Mxx_TXD1 indicates IEEE Std 802.3 pause frame support when high; no pause when low, as determined by reqnp in PortxControl. – Mxx_TXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, as determined by req10 in PortxControl. – Mxx_TXD3 is unused and is 0. M00_TXEN M01_TXEN M02_TXEN M03_TXEN M04_TXEN M05_TXEN M06_TXEN M07_TXEN D22 B17 B13 B8 H4 L1 V3 AE4 O None Transmit enable. Indicates valid transmit data on Mxx_TXDn. This signal is synchronous to Mxx_RFCLK. M00_TXER M01_TXER M02_TXER M03_TXER M04_TXER M05_TXER M06_TXER M07_TXER D21 A17 D11 C8 H3 N3 V2 AF4 O None Transmit error. Allows coding errors to be propagated across the MII. Mxx_TXER is asserted at the end of an under-running frame, enabling the TNETX4080 to force a coding error. |
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