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TNETX4080 数据表(PDF) 6 Page - Texas Instruments

部件名 TNETX4080
功能描述  ThunderSWITCH IIE 8-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  64 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX4080 数据表(HTML) 6 Page - Texas Instruments

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TNETX4080
ThunderSWITCH II™ 8-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Table 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued)
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
RESET
SAD0
SAD1
SCS
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7
M23
AF22
AE22
AD22
AF20
AE20
AD20
AC20
AF21
AE21
AD21
AC21
SDMA
SINT
SRDY
SRNW
SRXRDY
STXRDY
TCLK
TDI
TDO
TMS
TRST
VDD(2.5)
AF24
AF19
AF23
AC22
AE23
AD23
L24
M24
L23
M25
L25
B2
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
B25
C3
C24
D4
D9
D14
D18
D23
J4
J23
N4
P23
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(2.5)
VDD(3.3)
V4
V23
AC4
AC9
AC13
AC18
AC23
AD3
AD24
AE2
AE25
D8
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDD(3.3)
VDDa(2.5)
D13
D17
H23
K4
P4
W4
AC10
AC14
AC19
T23
Terminal Functions
IEEE Std 1149.1 (JTAG) interface
TERMINAL
I/O
INTERNAL
DESCRIPTION
NAME
NO.
I/O
RESISTOR
DESCRIPTION
TCLK
L24
I
Pullup
Test clock. Clocks state information and test data into and out of the TNETX4080 during operation
of the test port.
TDI
M24
I
Pullup
Test data input. Serially shifts test data and test instructions into the TNETX4080 during operation
of the test port. An internal pullup resistor is provided on TDI to ensure IEEE Std 1149.1 (JTAG)
compliance.
TDO
L23
O
None
Test data out. Serially shifts test data and test instructions out of the TNETX4080 during operation
of the test port.
TMS
M25
I
Pullup
Test mode select. Controls the state of the test-port controller. An internal pullup resistor is provided
on TMS to ensure IEEE Std 1149.1 (JTAG) compliance.
TRST
L25
I
Pullup
Test reset. Asynchronously resets the test-port controller. An internal pullup resistor is provided on
TRST to ensure IEEE Std 1149.1 (JTAG) compliance.
control logic interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
RESET
M23
I
Device reset. Asserted for a minimum of 100
µs after power supplies and clocks have stabilized. The system clock
must be operational during reset.
FLOW
AF8
O
Flow control. When flow control is activated (flow in SysControl = 1) and the number of free external memory
buffers is below the threshold indicated in FlowThreshold, FLOW is asserted.



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