ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

2

POST OFFICE BOX 1443

PCI

Bus

PCI

Bus Master

Control

FIFO

Registers

Multiplexed

SRAM

FIFO

Ethernet

LAN

Controller

10 / 100 Mbps

10 Base-T

Physical

Layer

Interface

10 Base-T

Ethernet

Media-

Independent

Interface

10 Base-5

(AUI)

Figure 1. ThunderLAN Architecture

description

ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet

solution with the flexibility to handle 100-Mbps Ethernet protocols as networking demands grow.

The TNETE100A, an implementation of the ThunderLAN architecture, is an intelligent protocol network

interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory and offers

a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer interface.

Modular support for 100 Base-T (IEEE 802.3u), and 100VG-AnyLAN (IEEE 802.12) is provided by a superset

of the industry-standard media independent interface (MII). ThunderLAN uses a single driver suite to support

multiple networking protocols.

The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz and is capable of

internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE100A

offers jumperless autoconfiguration using PCI configuration read / write cycles. Customizable configuration

registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE100A-based

systems to give their systems a unique identification code. The TNETE100A PCI interface, developed in

conjunction with other leaders in the semiconductor and computer industries, has been tested vigorously on

multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the

ThunderLAN drivers and ThunderLAN architecture use TI’s patented adaptive performance optimization (APO)

technology to adjust dynamically critical parameters for minimum latency, minimum host CPU utilization, and

maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are

used by automatically tuning the controller to the specific system in which it is operating.

The MII, an industry-standard interface for connecting a variety of external IEEE 802.3u physical layer

interfaces, is supported fully by the TNETE100A. In addition, the TNETE100A features an IEEE

802.12-compliant superset of the MII to allow for support of 100VG-AnyLAN physical layer interfaces. This

allows TNETE100A-based systems to support 100 Base-TX, 100 Base-FX, 100 Base-T4, and 100VG-AnyLAN

cabling schemes for maximum flexibility as each new physical-layer interface becomes available in the

marketplace.

An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for

minimum overhead related to multiple protocols, using common state machines to implement 95 percent of the

total PH. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields, and

interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and error

checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by

way of circular-buffer FIFOs in the FIFO SRAM.

ThunderLAN is the first multimedia-ready architecture and is capable of prioritized data regardless of the

selected protocol. The demand-priority protocol supports two priorities of frames: normal and priority

. The two

transmit channels provide independent host channels for these two frame types. Carrier-sense multiple access

with collision detection (CSMA / CD) protocols only support a single priority of frame, but the two channels can

be used to prioritize network access. All received frames pass through the single receive-channel.