ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

5

POST OFFICE BOX 1443

Pin Functions

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

TEST PORT

TCLK

124

I

Test clock. TCLK is used to clock state information and test data into and out of the device during

operation of the test port.

TDI

126

I

Test data input. TDI is used to shift test data and test instructions serially into the device during

operation of the test port.

TDO

125

O

Test data output. TDO is used to shift test data and test instructions serially out of the device during

operation of the test port.

TMS

123

I

Test mode select. TMS is used to control the state of the test port controller within TNETE100A.

TRST

121

I

Test reset. TRST is used for asynchronous reset of the test port controller.

PCI INTERFACE

PAD31

135

PAD30

137

PAD29

138

PAD28

140

I/O

PCI address / data bus Byte 3 (most significant) of the PCI address / data bus

PAD27

141

I/O

PCI address / data bus. Byte 3 (most significant) of the PCI address / data bus.

PAD26

143

PAD25

144

PAD24

1

PAD23

5

PAD22

7

PAD21

8

PAD20

9

I/O

PCI address / data bus Byte 2 of the PCI address / data bus

PAD19

11

I/O

PCI address / data bus. Byte 2 of the PCI address / data bus.

PAD18

12

PAD17

13

PAD16

15

PAD15

29

PAD14

30

PAD13

32

PAD12

33

I/O

PCI address / data bus Byte 1 of the PCI address / data bus

PAD11

35

I/O

PCI address / data bus. Byte 1 of the PCI address / data bus.

PAD10

36

PAD9

38

PAD8

39

† I = input, O = output, I / O = 3-state input / output