ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

6

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

PCI INTERFACE (CONTINUED)

PAD7

42

PAD6

43

PAD5

45

PAD4

46

I/O

PCI address / data bus Byte 0 (least significant) of the PCI address / data bus

PAD3

47

I/O

PCI address / data bus. Byte 0 (least significant) of the PCI address / data bus.

PAD2

49

PAD1

50

PAD0

51

PCLK

131

I

PCI clock. PCLK is the clock reference for all PCI bus operations. All other PCI pins except PRST and

PINTA are sampled on the rising edge of PCLK. All PCI bus timing parameters are defined with respect

to this edge.

PCLKRUN

53

I/O ‡

Clock run control. PCLKRUN is the active-low PCI clock request /grant signal that allows the

TNETE100A to indicate when an active PCI clock is required. (This is an open drain.)

PC / BE3

PC / BE2

PC / BE1

PC / BE0

2

16

28

41

I/O

PCI bus command and byte enables: PC / BE3 enables byte 3 (MSbyte) of the PCI address/data bus.

PC / BE2 enables byte 2 of PCI address / data bus.

PC / BE1 enables byte 1 of PCI address / data bus.

PC / BE0 enables byte 0 (LSbyte) of PCI address / data bus.

PDEVSEL

21

I/O

PCI device select. PDEVSEL indicates that the driving device has decoded one of its addresses as

the target of the current access. The TNETE100A drives PDEVSEL when it decodes an access to one

of its registers. As a bus master, the TNETE100A monitors PDEVSEL to detect accesses to illegal

memory addresses.

PFRAME

17

I/O

PCI cycle frame. PFRAME is driven by the active bus master to indicate the beginning and duration

of an access. PFRAME is asserted to indicate the start of a bus transaction and remains asserted

during the transaction, only being deasserted in the final data phase.

PGNT

132

I

PCI bus grant. PGNT is asserted by the system arbiter to indicate that the TNETE100A has been

granted control of the PCI bus.

PIDSEL

4

I

PCI initialization device select. PIDSEL is the chip select for access to PCI configuration registers.

PINTA

128

O/D

PCI interrupt. PINTA is the interrupt request from the TNETE100A. PCI interrupts are shared, so this

is an open-drain (wired-OR) output.

PIRDY

19

I/O

PCI initiator ready. PIRDY is driven by the active bus master to indicate that it is ready to complete the

current data phase of a transaction. A data phase is not completed until both PIRDY and PTRDY are

sampled asserted. When the TNETE100A is a bus master, it uses PIRDY to align incoming data on

reads or outgoing data on writes with its internal RAM-access synchronization (maximum one cycle

at the beginning of burst). When the TNETE100A is a bus slave, it extends the access appropriately

until both PIRDY and PTRDY are asserted.

PTRDY

20

I/O

PCI target ready. PTRDY is driven by the selected device (bus slave or target) to indicate that it is ready

to complete the current data phase of a transaction. A data phase is not completed until both PIRDY

and PTRDY are sampled asserted.

ThunderLAN uses PTRDY to ensure every direct I/O (DIO) operation is correctly interlocked.

PPAR

27

I/O

PCI parity. PPAR carries even parity across PAD[31:0] and PC / BE[3:0]. It is driven by the TNETE100A

during all address and write cycles as a bus master and during all read cycles as a bus slave.

PPERR

24

I/O

PCI parity error. PPERR indicates a data parity error on all PCI transactions except special cycles.

† I = input, I / O = 3-state input / output, O / D = open-drain output

‡ Open drain