TNETE110 datasheet(4/24 Pages) TI1

4 / 24 page

ThunderLAN

™ TNETE110

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS018B – MARCH 1995 - REVISED MAY 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

functional block diagram

EXLE

EALE

EOE

PFRAME

PTRDY

PIRDY

PSTOP

PDEVSEL

PIDSEL

PCI

Interface

(PCIIF)

Test-Access

Port

(TAP)

Config

& I/O

Memory

Registers

Config

EEPROM

Interface

BIOS

ROM / LED

Driver

Interface

DMA

Controller

FIFO

Pointer

Registers

(FPREGs)

FSRAM

(FIFO SRAM)

128-Byte

List

1.5K-Byte

Rx Buffer

0.75K-Byte

Tx Buffer

0.75K-Byte

Tx Buffer

PCLK

PCLKRUN

PRST

PINTA

PPERR

PSERR

PREQ

PGNT

PAD[31:0]

PC/BE[3:0]

EDCLK

EDIO

EAD[7:0]

Protocol

Handler

(PH)

10-Mbps

Ethernet

Physical

Layer

(PHY)

Interface

AXMTP

AXMTN

ARCVP

ARCVN

ACOLP

ACOLN

FXMTP

FXMTN

FRCVP

FRCVN

FXTL1

FXTL2

FIREF

FATEST

TRST

TMS

TCLK

TDO

TDI

TNETE110

( ThunderLAN)

PPAR

Address

and Data

BIOS ROM

and

LED I/F

Interface

Control

Error

Reporting

IEEE

1149.1

Test-

Access

Port

Configuration

EEPROM

Interface

Bus

Arbitration

System

Control

10 Base-T

Interface

AUI

Interface

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