AD9645 datasheet(21/36 Pages) AD

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Data Sheet

AD9645

Rev. 0 | Page 21 of 36

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9645 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typically

ac-coupled into the CLK+ and CLK− pins via a transformer or

capacitors. These pins are biased internally (see Figure 44) and

require no external bias.

Clock Input Options

The AD9645 has a flexible clock input structure. The clock input

can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless

of the type of signal being used, clock source jitter is of the most

concern, as described in the Jitter Considerations section.

Figure 57 and Figure 58 show two preferred methods for clocking

the AD9645 (at clock rates up to 1 GHz prior to the internal clock

divider). A low jitter clock source is converted from a single-ended

signal to a differential signal using either an RF transformer or an

RF balun.

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

Figure 57. Transformer-Coupled Differential Clock (Up to 200 MHz)

0.1µF

CLOCK

INPUT

0.1µF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 58. Balun-Coupled Differential Clock (Up to 1 GHz)

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 1 GHz, and the RF transformer configu-

ration is recommended for clock frequencies from 10 MHz

to 200 MHz. The back-to-back Schottky diodes across the

transformer/balun secondary winding limit clock excursions

into the AD9645 to approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock from

feeding through to other portions of the AD9645 while preserving

the fast rise and fall times of the signal that are critical to achieving

low jitter performance. However, the diode capacitance comes into

play at frequencies above 500 MHz. Care must be taken when

choosing the appropriate signal limiting diode.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 59. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

0Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

Figure 59. Differential PECL Sample Clock (Up to 1 GHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 60. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

0Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

Figure 60. Differential LVDS Sample Clock (Up to 1 GHz)

In some applications, it may be acceptable to drive the sample clock

inputs with a single-ended 1.8 V CMOS signal. In such applica-

tions, drive the CLK+ pin directly from a CMOS gate, and bypass

the CLK− pin to ground with a 0.1 μF capacitor (see Figure 61).

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 61. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9645 contains an input clock divider that can divide the

input clock by integer values from 1 to 8. To achieve a given sample

rate, the frequency of the externally applied clock must be multi-

plied by the divide value. The increased rate of the external clock

normally results in lower clock jitter, which is beneficial for IF

undersampling applications.

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