AD9645 datasheet(33/36 Pages) AD

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Data Sheet

AD9645

Rev. 0 | Page 33 of 36

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Interfacing to High Speed ADCs via SPI.

Device Index (Register 0x05)

There are certain features in the map that can be set indepen-

dently for each channel, whereas other features apply globally

to all channels (depending on context), regardless of which is

selected. Bits[1:0] in Register 0x05 can be used to select which

individual data channel is affected. The output clock channels

can be selected in Register 0x05, as well. A smaller subset of the

independent feature list can be applied to those devices.

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment they

are written. Setting Bit 0 of Register 0xFF high initializes the

settings in the ADC sample rate override register (Address 0x100).

Power Modes (Register 0x08)

Bits[7:2]—Open

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), both ADC channels are

active.

In power-down mode (Bits[1:0] = 01), the digital datapath clocks

are disabled while the digital datapath is reset. Outputs are disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks

and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), all the digital datapath clocks

and the outputs (where applicable) on the chip are reset, except the

SPI port. Note that the SPI is always left under control of the user;

that is, it is never automatically disabled or in reset (except by

power-on reset).

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct conversion

receivers, chopping in the first stage of the AD9645 is a feature

that can be enabled by setting Bit 2. In the frequency domain,

chopping translates offsets and other low frequency noise to

fCLK/2, where it can be filtered.

Bits[1:0]—Open

Output Mode (Register 0x14)

Bit 7—Open

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit selects the LVDS-IEEE (reduced range) option.

The default setting is LVDS-ANSI. When LVDS-ANSI or the

LVDS-IEEE reduced range link is selected, the user can select

the driver termination (see Table 17). The driver current is

automatically selected to give the proper output swing.

Table 17. LVDS-ANSI/LVDS-IEEE Options

Output

Mode,

Bit 6

Output

Mode

Output Driver

Termination

Output Driver

Current

LVDS-ANSI

User selectable

Automatically selected

to give proper swing

LVDS-IEEE

reduced

range link

User selectable

Automatically selected

to give proper swing

Bits[5:3]—Open

Bit 2—Output Invert

Setting this bit inverts the output bit stream.

Bit 1—Open

Bit 0—Output Format

By default, this bit is set to send the data output in twos

complement format. Clearing this bit to 0 changes the output

mode to offset binary.

Output Adjust (Register 0x15)

Bits[7:6]—Open

Bits[5:4]—Output Driver Termination

These bits allow the user to select the internal termination resistor.

Bits[3:1]—Open

Bit 0—Output Drive

Bit 0 of the output adjust register controls the drive strength on

the LVDS driver of the FCO and DCO outputs only. The default

values set the drive to 1×, or the drive can be increased to 2× by

setting the appropriate channel bit in Register 0x05 and then

setting Bit 0. These features cannot be used with the output

driver termination select. The termination selection takes

precedence over the 2× driver strength on FCO and DCO when

both the output driver termination and output drive are selected.

Output Phase (Register 0x16)

Bit 7—Open

Bits[6:4]—Input Clock Phase Adjust

See Table 18 for details.

Table 18. Input Clock Phase Adjust Options

Input Clock Phase Adjust,

Bits[6:4]

Number of Input Clock Cycles

of Phase Delay

000 (Default)

001

010

011

100

101

110

111

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