M41T00CAP

Operation

Doc ID 14557 Rev 5

9/27

3

Operation

by implementing a start condition followed by the correct slave address (D0h). The 8 bytes

contained in the device can then be accessed sequentially in the following order:

1.

Seconds register

2.

Minutes register

3.

Century/hours register

4.

Day register

5.

Date register

6.

Month register

7.

Year register

8.

Calibration register

address counter. Inputs to the device will not be recognized at this time to prevent erroneous

For more information on battery storage life refer to application note AN1012.

3.1

Wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a

bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must

be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

●

Data transfer may be initiated only when the bus is not busy.

●

During data transfer, the data line must remain stable whenever the clock line is high.

●

Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

3.2

Bus not busy

Both data and clock lines remain high.