M41T00CAP

Operation

Doc ID 14557 Rev 5

13/27

3.8

WRITE mode

In this mode the master transmitter transmits to the M41T00CAP slave receiver. Bus

protocol is shown in Figure 9. Following the START condition and slave address, a logic '0'

(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

address location on the reception of an acknowledge clock. The device slave receiver will

send an acknowledge clock to the master transmitter after it has received the slave address

and again after it has received the word address and after each data byte.

Figure 9.

WRITE mode sequence

3.9

Data retention mode

or WRITE cycles. Should the supply voltage decay, the power input will be switched from

AI00591

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS