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WM8741GEDS/V 数据表(PDF) 14 Page - Wolfson Microelectronics plc |
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WM8741GEDS/V 数据表(HTML) 14 Page - Wolfson Microelectronics plc |
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14 / 64 page ![]() WM8741 Production Data w PD, Rev 4.2, October 2009 14 CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 5 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DVDD = 3.3V, GND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT SCLK rising edge to LATCH rising edge tSCS 40 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 32 ns SCLK pulse width high tSCH 32 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns LATCH pulse width low tCSL 20 ns LATCH pulse width high tCSH 20 ns LATCH rising to SCLK rising tCSS 20 ns Table 4 Control Interface Timing – 3-Wire Serial Control Mode |
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