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WM8741GEDS/V 数据表(PDF) 15 Page - Wolfson Microelectronics plc |
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WM8741GEDS/V 数据表(HTML) 15 Page - Wolfson Microelectronics plc |
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15 / 64 page ![]() Production Data WM8741 w PD, Rev 4.2, October 2009 15 CONTROL INTERFACE TIMING – 2-WIRE MODE Figure 6 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT SCLK Frequency 0 5 MHz SCLK Low Pulse-Width tSCL 80 ns SCLK High Pulse-Width tSCH 80 us Hold Time (Start Condition) tHOL 600 ns Setup Time (Start Condition) tCSE 600 ns Data Setup Time tDSU 100 ns SDIN, SCLK Rise Time tRIS 300 ns SDIN, SCLK Fall Time tFAL 300 ns Setup Time (Stop Condition) tCSS 600 ns Data Hold Time tDHO 900 ns Max Pulse width of spikes that will be suppressed tPS 4 6 ns Table 5 Control Interface Timing – 2-wire Serial Control Mode |
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