Production Data

WM8501

w

PD, Rev 4.2, July 2009

13

HIGH PERFORMANCE MODE

On the rising edge of ENABLE, the DEEMPH pin is sampled. If it is low the device powers up

normally. If it is high the device goes into a high performance and high power consumption state.

Once ENABLE is high, DEEMPH controls the selection of the de-emphasis filter.

INPUT AUDIO FORMAT SELECTION

FORMAT (pin 13) controls the data input format.

FORMAT

INPUT DATA MODE

0

16 bit right justified

1

Table 2 Input Audio Format Selection

Notes:

1.

high for a minimum of data width BCLKs and low for a minimum of data width BCLKs,

unless Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the

most significant 24 bits will be used by the internal processing.

2.

If exactly 16 BCLK cycles occur in both the low and high period of LRCLK the WM8501 will

assume the data is 16-bit and accept the data accordingly.

INPUT DSP FORMAT SELECTION

FORMAT

50% LRCLK DUTY CYCLE

LRCLK of 4 BCLK or Less Duration

0

16 bit

(MSB-first, right justified)

DSP format –mode B

1

(Philips serial data protocol)

DSP format –mode A

Table 3 DSP Interface Formats

DE-EMPHASIS CONTROL

DEEMPH (pin 12) is an input control for selection of de-emphasis filtering to be applied.

DEEMPH

DE-EMPHASIS

0

Off

1

On

Table 4 De-emphasis Control