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ICX205 数据表(PDF) 2 Page - Sony Corporation |
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ICX205 数据表(HTML) 2 Page - Sony Corporation |
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2 / 22 page ![]() – 2 – ICX205AL Pin No. Symbol Description Pin No. Symbol Description 1 2 3 4 5 6 7 8 9 10 V φ1 V φ2A V φ2B V φ3 NC NC GND NC GND VOUT Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND GND Signal output 11 12 13 14 15 16 17 18 19 20 VDD GND φSUB NC CSUB NC VL φRG H φ1 H φ2 Supply voltage GND Substrate clock Substrate bias∗1 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Pin Description Note) Horizontal register 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 Note) : Photo sensor Block Diagram and Pin Configuration (Top View) ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. |
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