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ICX205 数据表(PDF) 4 Page - Sony Corporation |
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ICX205 数据表(HTML) 4 Page - Sony Corporation |
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4 / 22 page ![]() – 4 – ICX205AL Clock Voltage Conditions Item Readout clock voltage VVT VVH02A VVH1, VVH2A, VVH2B, VVH3 VVL1, VVL2A, VVL2B, VVL3 V φ1, Vφ2A, V φ2B, Vφ3 | VVL1 – VVL3 | VVHH VVHL VVLH VVLL V φH VHL V φRG VRGLH – VRGLL VRGL – VRGLm V φSUB 14.55 –0.05 –0.2 –8.4 7.6 4.75 –0.05 3.0 22.15 15.0 0 0 –8.0 8.0 5.0 0 3.3 23.0 15.45 0.05 0.05 –7.6 8.4 0.1 0.9 1.3 1.0 0.9 5.25 0.05 5.5 0.4 0.5 23.85 V V V V V V V V V V V V V V V V 1 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 VVH = VVH02A VVL = (VVL1 + VVL3)/2 High-level coupling High-level coupling Low-level coupling Low-level coupling Low-level coupling Low-level coupling Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Vertical transfer clock voltage Symbol Min. Typ. Max. Unit Waveform diagram Remarks Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock VDD VL φSUB φRG 14.55 15.0 ∗1 ∗2 ∗2 15.45 V Symbol Min. Typ. Max. Unit Remarks DC Characteristics Item Supply current IDD 5.5 mA Symbol Min. Typ. Max. Unit Remarks ∗1 V L setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. |
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