RT8205CGQW datasheet(25/28 Pages) RICHTEK

25 / 28 page

RT8205A/B/C

DS8205A/B/C-06 July 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

P-P

LOAD(MAX)

ESR

≤

In non-CPU applications, the output capacitor's size

depends on how much ESR is needed to maintain an

acceptable level of output voltage ripple :

where VP-P is the peak-to-peak output voltage ripple.

Organic semiconductor capacitor(s) or specialty polymer

capacitor(s) are recommended.

For low input-to-output voltage differentials (VIN / VOUTx

< 2), additional output capacitance is required to maintain

stability and good efficiency in ultrasonic mode.

The amount of overshoot due to stored inductor energy

can be calculated as :

PEAK

SOAR

OUT

OUTx

)

≤

××

where IPEAK is the peak inductor current.

Although Mach ResponseTM DRVTM dual ramp valley mode

provides many advantages such as ease-of-use, minimum

external component configuration, and extremely short

response time, due to not employing an error amplifier in

the loop, a sufficient feedback signal needs to be provided

by an external circuit to reduce the jitter level. The required

signal level is approximately 15mV at the comparing point.

This generates VRipple = (VOUT / 2) x 15mV at the output

node. The output capacitor ESR should meet this

requirement.

ESR

OUT

ESR C

≤

××

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :

Do not put high-value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high- ESR zero

frequency and cause erratic, unstable operation. However,

it is easy to add enough series resistance by placing the

capacitors a couple of inches downstream from the

inductor and connecting VOUTx or the FBx divider close

to the inductor.

Unstable operation manifests itself in two related and

distinctly different ways: double-pulsing and feedback loop

instability.

Double-pulsing occurs due to noise on the output or

because the ESR is so low that there is not enough voltage

ramp in the output voltage signal. This “fools” the error

comparator into triggering a new cycle immediately after

the 300ns minimum off-time period has expired. Double-

pulsing is more annoying than harmful, resulting in nothing

worse than increased output ripple. However, it may

indicate the possible presence of loop instability, which

is caused by insufficient ESR.

Loop instability can result in oscillations at the output

after line or load perturbations that can trip the overvoltage

protection latch or cause the output voltage to fall below

the tolerance limit.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully observe

the output-voltage-ripple envelope for overshoot and ringing.

It helps to simultaneously monitor the inductor current

with an AC current probe. Do not allow more than one

cycle of ringing after the initial step-response under- or

overshoot.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = ( TJ(MAX) - TA ) /

θJA

Where TJ(MAX) is the maximum operation junction

temperature, TA is the ambient temperature and the

θJAis

the junction to ambient thermal resistance.

For recommended operating conditions specification, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance

θJA is layout dependent. For

WQFN-24L 4x4 packages, the thermal resistance

θJA is

°C/W on the standard JEDEC 51-7 four layers thermal

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