TTP/C-C1 Communications Controller Data Sheet

AS8201

Rev. NC, October 1999

Page 8 of 13

Austria Mikro Systeme International AG

lines signal to host CPU the global synchronous time of the TTP network and determine when

to deliver, resp. to fetch data from the host interface. One of the lines may be connected to a

interrupt inputs of the host CPU.

Pin Name

mode

width

comment

RAM_ADDRESS

in

11

DPRAM address bus, 11 bit

RAM_DATA

inout (tri)

16

DPRAM data bus, 16 bit

RAM_CEB

in

1

DPRAM chip enable

RAM_WEB

in

1

DPRAM write enable

RAM_OEB

in

1

DPRAM output enable

RAM_READYB

out

1

DPRAM ready

TIME_OVERFLOW

out

1

overflow of global time

TIME_SIGNAL

out

1

CNI time signal

TIME_TICK

out

1

macrotick

Table 2 Host Interface Ports

microtick

t

ct

ram_data

XXX

t

dv

ram_address

XXX

t

a

ram_ceb

t

ce

t

rwct

address stable

ram_web

Figure 3: Read Cycle Timing

Addresses and RAM_WEB have to be stable before the falling edge of RAM_CEB. RAM_CEB

has to be applied for 2 microticks. Addresses and RAM_WEB have to be applied for 3

microticks. Data can be read from RAM_DATA after 6 microticks. RAM_OEB drives the result

of the (last) read operation to the RAM_DATA bus.