TTP/C-C1 Communications Controller Data Sheet

AS8201

Rev. NC, October 1999

Page 7 of 13

Austria Mikro Systeme International AG

AC Characteristics

Clock applied at XOUT0, resp. XOUT1.

PARAMETER

SYMBOL

PIN

MIN

MAX

NOTE

data in setup

time

tsetup

all IN,

all IO

20 ns

vs. Falling edge of clk @XOUT0, XOUT1

data output

valid

tdav

all OUT,

all IO

35 ns

vs. rising edge of clk @ XOUT0, XOUT1

Application Informatio n

ROM Interface

Pin name

mode

width

comment

ROM_DATA

inout (tri)

16

ROM data bus

ROM_ADDRESS

out

17

ROM address bus

ROM_CEB

out

1

ROM chip enable

ROM_WEB

out

1

ROM write enable

ROM_OEB

out

1

ROM output enable

ROM_READY

in

1

ROM ready

ROM_RESETB

out

1

external reset line

Table 1 ROM Interface Ports

The timing and behaviour of the ROM Interface is designed to operate with the AM29F200

Flash EPROM or compatible devices. For detailed timing information see [AM29F200]

2 shows the connection between TTP/C-C1 controller and the AM29F200 Flash. The contents

of the Flash memory is loaded into the instruction memory by a boot sequencer automatically

after power on.

AM29F200

TTA-C1

RY/BY

RESET

WE

CE

OE

A0-A16

DQ0-DQ15

BYTE

VCC

rom_resetb

rom_web

rom_ceb

rom_oeb

rom_address

rom_ready

rom_data

Figure 2 ROM Interface

2

Host CPU Interface

The host CPU interface also referred as CNI (controller network interface) connects the

application circuitry to the TTP/C network. As shown in Table 2 all RAM_-lines provide

asynchronous read/write access to a dual ported RAM. There are no setup/hold constraints

referred to the microtick (main clock “clk”). The signals have to be applied for certain duration

according to Table 3. So, the applied signals get synchronised with the microtick. The TIME_-