ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet

ASCell3911

Rev. A, February 2000

Page 11 of 13

Austria Mikro Systeme International AG

DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)

VIH

High level input voltage

VDD-0,5

-

V

VIL

Low level input voltage

-

0,3

V

IIH

High level input current

VIH= VDD

1

µA

IIL

Low level input current

VIL =0 V

-1

µA

WAKEUP (µC clear output / transmitter power down input)

VOH

High level output voltage

IOH = -1mA

VDD-0,5

-

V

VOL

Low level output voltage

IOL = 1mA

-

0,3

V

VIH

High level input voltage

VDD-0,5

-

V

VIL

Low level input voltage

-

0,3

V

IIH

High level input current

VIH = VDD

1

µA

IIL

Low level input current

VIL =0 V; Due to

internal pull-up

-40

µA

2.4.1

µController Interface

Symbol

Parameter

Conditions / Notes

Min

Typ

Max

Units

FSK Data Bit duration

tbd

s

Time between Wake up and Data

Enable

Data input prepared to

receive data

tbd

s

Time between Data Enable and

Data

Data input prepared to

receive data

tbd

s

Time between Data and Data

Enable

Start-up and lock PLL

tbd

s

Time between Data Enable and

Transmit

Start-up and lock PLL

tbd

s

Time between Wake up and

Transmit start

tbd

s

Time that CLK output stays ac-

tbd

s

Power-On-Reset threshold volt-

age

RESET invalid when Vdd <

1,6

1,8

V

Power-On-Reset duration

2

10

ms

Power-On-Reset output

1,2

V

3

Pin Description

Note: pin ordering is preliminary - will be fixed at fab-in.

Pin

Name

Type

Description

1

RF+

A

Power amplifier output (open collector)

2

RF-

A

Power amplifier output (open collector)

3

PAGND

P

Power amplifier ground