ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet

ASCell3911

Rev. A, February 2000

Page 5 of 13

Austria Mikro Systeme International AG

1.4.1 Duty-Cycle Operation

In certain countries, it is required to reduce the average transmit power but it is allowed to keep

the peak power high. Therefore a duty-cycled operation mode is implemented in the ASCell3911.

By selecting this operation mode, the duty cycle of the transmit signal is set to 50%, related to an

observation interval of 10 ms. This function is be implemented in the burst interference resistant

protocol encoder. The duty cycle operation is set via the bit duty cycle operation (DCO).

Note: DCO is one bit of the control information.

1.4.2 Transmission Modi

The ASCell3911 supports two different transmission modii:

• The event oriented Single Message Transmission (SMT) where four times alternate syn-

chronization and data packets are transmitted. Due to the limited transmission time this

mode needs less power than CMT but supports no direct information about the duration of a

transmitted command. The bit SMT/CMT is “L” for this mode.

• The status oriented Continuous Message Transmission (CMT) where alternate synchroniza-

tion and data packets are transmitted as long as one button is pressed. This mode is less

power efficient than SMT but the duration of a command can be directly transported by the

duration of the transmission power. The bit SMT/CMT is “H” for this mode.

Note: SMT/CMT is one bit of the control information.

1.5 Driving Amplifier

The driving amplifier has a differential open collector output optimized for driving of small, sym-

of the connected load impedance. With a 2 k

Ω differential load a nominal peak output power (to

the antenna) of

≈2 mW is obtained. Please note that the finally radiated power (from antenna) is

lower and strongly dependent on the efficiency (function of the size) of the antenna to be used.

1.6 µC Interface and Power Management

The ASCell3911 contains a direct interface to a micro controller (

µC). The µC interface of the

ASCell3911 consists of the following five pins:

”Transmit data input” (DATA).

“Active ”H” transmit data enable” (D_EN).

”Transmit data clock input” (D_CLK).

”Active ”L” µC reset output/transmitter wakeup end input” (WAKEUP).

”µC clock output/active ”L” start-up input” (µC_CLK).

These lines support the µC with the required reset and clock signals and control the ASCell3911

internal power on/off circuit, which wakes up and shuts down the whole transmitter consisting of

the ASCell3911 and the µC.

Figure 3 shows a typical interconnection of the ASCell3911 with a typical µC. Figure 4 presents

a related timing for power up and down of the transmitter.