41594B datasheet(89/372 Pages) MICROCHIP

89 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 89

PIC12LF1840T48A

9.0

POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a

SLEEP instruction.

Upon entering Sleep mode, the following conditions

exist:

WDT will be cleared but keeps running, if

enabled for operation during Sleep.

PD bit of the STATUS register is cleared.

TO bit of the STATUS register is set.

CPU clock is disabled.

31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

Timer1 oscillator is unaffected and peripherals

that operate from it may continue operation in

Sleep.

ADC is unaffected, if the dedicated FRC clock is

selected.

Capacitive Sensing oscillator is unaffected.

I/O ports maintain the status they had before

SLEEP was executed (driving high, low or high-

impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following condi-

tions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include modules such as the DAC and FVR

modules.

See

Section 17.0

“Digital-to-Analog

Converter (DAC) Module” and Section 14.0 “Fixed

Voltage Reference (FVR)” for more information on

these modules.

9.1

Wake-up from Sleep

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin, if enabled

BOR Reset, if enabled

POR Reset

Watchdog Timer, if enabled

Any external interrupt

Interrupts by peripherals capable of running dur-

ing Sleep (see individual peripheral for more

information)

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section 7.10

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP instruction, the device will call the Interrupt Ser-

vice Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

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