41594B datasheet(117/372 Pages) MICROCHIP

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 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 117

PIC12LF1840T48A

13.0 INTERRUPT-ON-CHANGE

The PORTA pins can be configured to operate as

Interrupt-On-Change (IOC) pins. An interrupt can be

generated by detecting a signal that has either a rising

edge or a falling edge. Any individual PORTA pin, or

combination of PORTA pins, can be configured to

generate an interrupt. The interrupt-on-change module

has the following features:

• Interrupt-on-Change enable (Master Switch)

• Individual pin configuration

• Rising and falling edge detection

• Individual pin interrupt flags

Figure 13-1 is a block diagram of the IOC module.

13.1

Enabling the Module

To allow individual PORTA pins to generate an interrupt,

the IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

13.2

Individual Pin Configuration

For each PORTA pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated IOCAPx bit of the IOCAP

the associated IOCANx bit of the IOCAN register is set.

A pin can be configured to detect rising and falling

edges simultaneously by setting both the IOCAPx bit

and the IOCANx bit of the IOCAP and IOCAN registers,

respectively.

13.3

Interrupt Flags

The IOCAFx bits located in the IOCAF register are

status flags that correspond to the interrupt-on-change

pins of PORTA. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCIE

bit is set. The IOCIF bit of the INTCON register reflects

the status of all IOCAFx bits.

13.4

Clearing Interrupt Flags

The individual status flags, (IOCAFx bits), can be

cleared by resetting them to zero. If another edge is

detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 13-1:

13.5

Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCAF

executed out of Sleep.

FIGURE 13-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM

MOVLW

0xff

XORWF

IOCAF, W

ANDWF

IOCAF, F

RAx

From all other IOCAFx

individual pin detectors

IOCANx

IOCAPx

Q2 Clock Cycle

IOCIE

IOC Interrupt to

CPU Core

IOCAFx

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