DA6512.000

11 July, 2012

7 (26)

REGISTER AND EEPROM DATA ADDRESSES

Table 1.

Register and EEPROM data addresses

A7

A6

A5

A4

A3

A2

A1

A0

I2C

BUS

HEX

SPI BUS

HEX

W=write

R=read

Description

Note

A7

1

0

0

0

0

0

X

C0…C1

W: 40…41

R: C0…C1

EEPROM; free for any

data

E

A7

1

0

0

0

0

1

0

C2

W: 42

R: C2

EEPROM; free for any

data

E

A7

1

0

0

0

0

1

1

C3

W: 43

R: C3

EEPROM; CS capacitor

matrix trim data

E+T

A7

1

0

0

0

1

0

0

C4

W: 44

R: C4

EEPROM; CR capacitor

matrix trim data

E+T

A7

1

0

0

0

1

0

1

C5

W: 45

R: C5

EEPROM; Gain trim

data

E+T

A7

1

0

0

0

1

1

0

C6

W: 46

R: C6

EEPROM; Oscillator

frequency trim data

E+T

A7

1

0

0

0

1

1

1

C7

W: 47

R: C7

EEPROM; free for any

data

E

A7

1

0

0

1

X

X

X

C8…CF

W: 48…4F

R: C8…CF

EEPROM; free for any

data

E

A7

1

0

1

X

X

X

X

D0…DF

W: 50…5F

R: D0…DF

EEPROM; free for any

data

E

A7

1

1

0

0

0

0

0

E0

W: 60

R: E0

Reset register; no data,

only addressed for reset

R

A7

1

1

0

0

0

0

1

E1

W: 61

R: E1

Test register

R

A7

1

1

0

0

0

1

0

E2

W: 62

R: E2

Measurement control

register

R

A7

1

1

0

0

0

1

1

E3

W: 63

R: E3

CS capacitor matrix

register

R+T

A7

1

1

0

0

1

0

0

E4

W: 64

R: E4

CR capacitor matrix

register

R+T

A7

1

1

0

0

1

0

1

E5

W: 65

R: E5

Gain register

R+T

A7

1

1

0

0

1

1

0

E6

W: 66

R: E6

Oscillator frequency

control register

R+T

A7

1

1

0

1

0

1

0

EA

W: 6A

R: EA

1st (MSB) byte of the

conversion result

R

A7

1

1

0

1

0

1

1

EB

W: 6B

R: EB

2nd (LSB) byte of the

conversion result

R

A7

1

1

0

1

1

0

1

ED

W: 6D

R: ED

Status register for

EEPROM

R

A7

1

1

0

1

1

1

0

EE

W: 6E

R: EE

Trimming control

register

R

X = Don’t care, E = EEPROM, R= Register, T = Trim data

Note:

When using the SPI serial interface the register address bit A7 is also used for selecting write (A7= 0) or read (A7=1) operation. For

the I