AD6623AS datasheet(21/40 Pages) AD

21 / 40 page

REV. 0

AD6623

–21–

–15)

2, or 0.00006103515625. The register values, in hexadecimal,

and the corresponding coefficient weight from positive full-scale

through zero to negative full-scale is illustrated in Table X.

Table X. Coefficient Weights

Coefficient Weight

0x7FFF

1.999938964844

0x0001

0.00006103515625

0x0000

0xFFFF

–0.00006103515625

0x8001

–1.999938964844

0x8000

–2

Table XI shows the recommended b1 and b2 coefficients for the

respective oversampling rate.

Table XI. b1 and b2 Coefficients

Oversampling

–1.45514

0.57832

–1.56195

0.64526

–1.63412

0.69414

–1.72513

0.76047

SCALE AND RAMP

Scale factors can be range from 0 to [CHF]–1/[CHF] with a

resolution 1/[CHF]

FINE SCALING

AD6623 allows fine scaling of the RCF output signal. A scale

factor of 12 to 14 bits is available through the Microport. The

Microport fine scale factor is located in Channel Register 0xn0E.

RCF POWER RAMPING

The output of the RCF will be multiplied by a 14-bit ramping

profile before entering the CIC filters. It is a RAM program-

mable engine that starts indexing through ramping coefficients

when the RAMP bit works its way through the chain. It will then

count a programmable number of samples and then RAMP down

in reverse order. This will allow the ramping values to update at

a modest rate relative to the DAC and still contain the spectral

leakage associated with the ramping. A user should provide

through the MicroPort the ramping coefficient values, the number

of samples to ramp up, and one bit to define the air-interface

standard. The programmable power ramp up/down unit allows

power ramping on time-slot basis as specified from some wireless

transmission technologies (e.g, TDMA).

CASCADED INTEGRATOR COMB (CIC)

INTERPOLATING FILTERS

The I and Q outputs of the RCF stage are interpolated by two

cascaded integrator comb (CIC) filters. The CIC section is sepa-

rated into three discrete blocks: a fifth order filter (CIC5), a second

order resampling filter (rCIC2), and a scaling block (CIC Scaling).

The CIC5 and rCIC2 blocks each exhibit a gain that changes with

respect to their rate change factors, LrCIC2, MrCIC2 and LCIC5. The

product of these gains must be compensated for in a shared CIC

Scaling block and can be done to within 6 dB The remaining

compensation can come from the RCF (in the form of coeffi-

cient scaling) or the fine scaling unit.

SERIAL

8PSK

MAPPER

SPH

[2:0]

[3:0]

PHASE

[3:0]

RPH

Figure 24. 3

π/8-8-PSK Mapper

MSK Look-Up Table

The MSK Look-Up Table mode for the RCF is selected in Control

pulse-shaping based on four symbols of impulse response. For the

MSK Mode (3, [16] bits), the serial input format is 11 bits of scaling

(MSB first) followed by 1 bit of data. The 11 bits can be used to

scale the input data.

GMSK Look-Up Table

The GMSK Look-Up Table mode for the RCF is selected in Control

pulse-shaping based on four symbols of impulse response. For the

GMSK Mode (3, [16] bits), the serial input format is 11 bits of

scaling (MSB first) followed by 1 bit of data. The 11 bits can be used

to scale the input data.

QPSK Look-Up Table

The QPSK Filter mode for the RCF is selected in Control

linear pulse-shaping based on filter impulse response up to 12

symbols. For the QPSK Mode (3, [16]bits), the serial input format

is 13 bits of scaling (MSB first) followed by one bit I and then

one bit Q. The 13 bits can be used to scale the input data.

PHASE EQUALIZER

The IS-95 Standard includes a phase equalizer after matched

filtering at the baseband transmit side of a base station. This

filter pre-distorts the transmitted signal at the base station in

order to compensate for the distortion introduced to the received

signal by the analog baseband filtering in a handset. The AD6623

includes this functionality in the form of an Infinite Impulse

Response (IIR) all-pass filter in the RCF. This Phase Equalizer

pre-distort filter has the following transfer function:

b z

zb z

()

== ++

(9)

Z–1

X(z)

Y(z)

Figure 25. Second Order All-Pass IIR Filter

The Phase Equalizer is enabled/disabled in Control Register

0xn0D Bit 5. The coefficients b1 and b2 are located in Control

Registers 0xn10 and 0xn11 respectively

The format for b1 and b2 is two’s complement fractional binary

with a range of (–2, 2). With one bit for sign at most significant bit

position there are 15 bits for magnitude. The value of one bit is

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