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AD6623

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PRODUCT DESCRIPTION

The AD6623 is a 4-channel Transmit Signal Processor (TSP)

that creates high bandwidth data for Transmit Digital-to-Analog

Converters (TxDACs) from baseband data provided by a Digital

Signal Processor (DSP). Modern TxDACs have achieved suffi-

ciently high sampling rates, analog bandwidth, and dynamic range

to create the first Intermediate Frequency (IF) directly. The

AD6623 synthesizes multicarrier and multistandard digital signals

to drive these TxDACs. The RAM-based architecture allows easy

reconfiguration for multimode applications. Modulation, pulse-

shaping and anti-imaging filters, static equalization, and tuning

functions are combined in a single, cost-effective device. Digital

IF signal processing provides repeatable manufacturing, higher

accuracy, and more flexibility than comparable high dynamic

range analog designs.

The AD6623 has four identical digital TSPs complete with synchro-

nization circuitry and cascadable wideband channel summation.

AD6623 is pin compatible to AD6622 and can operate in AD6622-

compatible control register mode.

The AD6623 utilizes a 3.3 V I/O power supply and a 2.5 V core

power supply. All I/O pins are 5 V tolerant. All control registers

and coefficient values are programmed through a generic micro-

processor interface. Intel and Motorola microprocessor bus modes

are supported. All inputs and outputs are LVCMOS compatible.

FUNCTIONAL OVERVIEW

Each TSP has five cascaded signal processing elements: a pro-

grammable interpolating RAM Coefficient Filter (RCF), a

programmable Scale and Power Ramp, a programmable fifth order

Cascaded Integrator Comb (CIC5) interpolating filter, a flexible

second order Resampling Cascaded Integrator Comb filter (rCIC2),

and a Numerically Controlled Oscillator/Tuner (NCO).

The outputs of the four TSPs are summed and scaled on-chip.

In multicarrier wideband transmitters, a bidirectional bus allows

the Parallel (wideband) IF Input/Output to drive a second DAC.

In this operational mode two AD6623 channels drive one DAC

and the other two AD6623 channels drive a second DAC. Mul-

tiple AD6623s may be combined by driving the INOUT[17:0] of

the succeeding with the OUT[17:0] of the preceding chip. The

INOUT[17:0] can alternatively be masked off by software to

allow preceding AD6623’s outputs to be ignored.

Each channel accepts input data from independent serial ports

that may be connected directly to the serial port of Digital Signal

Processor (DSP) chips.

The RCF implements any one of the following functions:

Interpolating Finite Impulse Response (FIR) filter, /4-DQPSK

modulator, 8-PSK modulator, or 3

/8-8-PSK modulator, GMSK

modulator, and QPSK modulator. Each AD6623 channel can

be dynamically switched between the GMSK modulation mode

and the 3

/8-8-PSK modulation mode in order to support the

GSM/EDGE standard. The RCF also implements an Allpass

Phase Equalizer (APE) which meets the requirements of IS-95-A/B

standard (CDMA transmission).

The programmable Scale and Power Ramp block allows power

ramping on a time-slot basis as specified for some air-interface

standards (e.g., GSM, EDGE). A fine scaling unit at the pro-

grammable FIR filter output allows an easy signal amplitude

level adjustment on time slot basis.

The CIC5 provides integer rate interpolation from 1 to 32 and

coarse anti-image filtering. The rCIC2 provides fractional rate

interpolation from 1 to 4096 in steps of 1/512. The wide range

of interpolation factors in each CIC filter stage and a highly

flexible resampler incorporated into rCIC2 makes the AD6623

useful for creating both narrowband and wideband carriers in a

high-speed sample stream.

The high resolution 32-bit NCO allows flexibility in frequency

planning and supports both digital and analog air interface stan-

dards. The high speed NCO tunes the interpolated complex signal

from the rCIC2 to an IF channel. The result may be real or com-

plex. Multicarrier phase synchronization pins and phase offset

registers allow intelligent management of the relative phase of

independent RF channels. This capability supports the require-

ments for phased array antenna architectures and management

of the wideband peak/power ratio to minimize clipping at the DAC.

The wideband Output Ports can deliver real or complex data.

Complex words are interleaved into real (I) and imaginary (Q)

parts at half the master clock rate.

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