AD6623AS datasheet(28/40 Pages) AD

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AD6623

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Beam

A change in phase for a particular channel and can be synchronized

with respect to other channels or AD6623s. This change in phase

can be synchronized via microprocessor control or an external

Sync signal.

To set the amplitude without synchronization the following

method should be used.

Set Phase No Beam

1. Set the NCO Phase Offset Update Hold-Off Counter (0xn05)

to 0.

2. Load the appropriate NCO Phase Offset (0xn04). The NCO

Phase Offset will be immediately loaded.

Beam with Soft Sync

The AD6623 includes the ability to synchronize a change in NCO

phase of multiple channels or chips under microprocessor control.

The NCO Phase Offset Update Hold-Off Counter in conjunction

with the Beam bit and the Sync bit (Ext Address 5) allow this

synchronization. Basically the NCO Phase Offset Update Hold-

Off Counter delays the new phase from being loaded into the

NCO/RCF by its value (number of AD6623 CLKs). The following

method is used to synchronize a beam in phase of multiple channels

via microprocessor control.

1. Write the NCO Phase Offset Update Hold-Off Counter (0xn05)

to the appropriate value (greater than 1 and less then 2

16–1).

2. Write the NCO Phase Offset register(s) to the new desired

phase and amplitude.

3. Write the beam bit and the Sync(s) bit high (Ext Address 5).

4. This starts the NCO Phase Offset Update Hold-Off Counter

counting down. The counter is clocked with the AD6623

CLK signal. When it reaches a count of one the new phase is

loaded into the NCO.

Beam with Pin Sync

A Sync pin is provided on the AD6623 to provide the most

accurate synchronization, especially between multiple AD6623s.

Synchronization of beaming to a new NCO Phase Offset with an

external signal is accomplished using the following method.

1. Write the NCO Phase Offset Hold-Off (0xn05) counter(s) to

the appropriate value (greater than 1 and less than 2

16–1).

2. Write the NCO Phase Offset register(s) to the new desired

phase and amplitude.

3. Set the Beam on Pin Sync bit and the appropriate Sync Pin

Enable high (0xn01).

4. When the Sync pin is sampled high by the AD6623 CLK this

enables the count down of the NCO Phase Offset Hold-Off

counter. The counter is clocked with the AD6623 CLK signal.

When it reaches a count of one the new phase is loaded into

the NCO registers.

JTAG INTERFACE

The AD6623 supports a subset of IEEE Standard 1149.1 specifica-

tion. For additional details of the standard, please see IEEE Standard

Test Access Port and Boundary-Scan Architecture, IEEE-1149

publication from IEEE.

The AD6623 has five pins associated with the JTAG interface.

These pins are used to access the on-chip Test Access Port and

are listed in Table XVII.

Table XVII. Test Access Port Pins

Name

Pin Number

Description

TRST

100

Test Access Port Reset

TCK

101

Test Clock

TMS

106

Test Access Port Mode Select

TDI

108

Test Data Input

TDO

107

Test Data Output

Note that TCK and TDI are internally pulled down which is

opposite of IEEE Standard 1149.1. These pins may be connected

to external pull-up resistors, with the associated additional current

draw through the pull-ups, or left unconnected.

The AD6623 supports four op codes are shown in Table XVIII.

These instructions set the mode of the JTAG interface.

Table XVIII. Op Codes

Instruction

Op Code

IDCODE

BYPASS

SAMPLE/PRELOAD

EXTEST

The Vendor Identification Code (Table XIX) can be accessed

through the IDCODE instruction and has the following format.

Table XIX. Vendor Identification Code

MSB

Part

Manufacturer

LSB

Version Number

ID Number

Mandatory

0000

0010 0111 1000 0000

000 1110 0101

A BSDL file for this device is available from Analog Devices, Inc.

Contact Analog Devices for more information.

SCALING

Proper scaling of the wideband output is critical to maximize the

spurious and noise performance of the AD6623. A relatively small

overflow anywhere in the data path can cause the spurious free

dynamic range to drop precipitously. Scaling down the output

levels also reduces dynamic range relative to an approximately

constant noise floor. A well-balanced scaling plan at each point

in the signal path will be rewarded with optimum performance.

The scaling plan can be separated into two parts: multicarrier

scaling and single-carrier scaling.

Multicarrier Scaling

An arbitrary number of AD6623s can be cascaded to create a

composite digital IF with many carriers. As the number of carriers

increases, the peak to RMS ratio of the composite digital IF will

increase as well. It is possible and beneficial to limit the peak to

RMS ratio through careful frequency planning and controlled

phase offsets. Nevertheless, in most cases with a large number of

carriers, the worst-case peak is an unlikely event.

The AD6623 immediately preceding the DAC can be programmed

to clip rather than wrap around (see the Summation Block de-

scription). For a large number of carriers, a rare but finite chance of

clipping at the AD6623 wideband output will result in superior

dynamic range compared to lowering each carrier level until

clipping is impossible. This will also be the case for most DACs.

Through analysis or experimentation, an optimal output level of

individual carriers can be determined for any particular DAC.

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