REV. A

AD7013

–7–

RECEIVE SECTION TIMING

(V

T

MCLK (I)

RxCLK (O)

RxFRAME (O)

RxDATA (O)

I MSB

I LSB

1

t

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

15-BIT

I WORD

I/Q

FLAG BIT

15-BIT

Q WORD

Q LSB

Q MSB

0

I/Q

FLAG BIT

Q LSB

DxCLK (O)

I MSB

FINAL IQ PAIR PRIOR

TO POWER DOWN

CR14

NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT

0

I LSB

1

Q MSB

The last DxCLK edge which is

used to write to Command Reg

One, setting CR14 to One

The last DxCLK edge which is

used to write to Command Reg

One, setting CR14 to Zero

t

25

t

16

Figure 3. Receive Serial Interface Timing with 4

× Sampling of the Symbol Rate (CR10 = 1)

Limit at

Parameter

T

Units

Description

t

16

Power-Up Receive to RxCLK

10240t

1

ns max

CR13 = 0, Rx Offset Autocalibration On

6144t

1

ns max

CR13 = 1, Rx Offset Autocalibration Off

t

17

30

ns min

Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge

85

ns max

t

18

2t

1

ns

RxCLK Cycle Time; CR10 = 1; 4

× Sampling of the Symbol Rate

t

19

t

ns min

RxCLK High Pulse Width; CR10 = 1

t

20

t

ns min

RxCLK Low Pulse Width; CR10 = 1

t

21

–10

ns min

RxCLK Rising Edge to RxFRAME Rising Edge

10

ns max

t

22

32t

1

ns

RxFRAME Cycle Time; CR10 = 1

t

23

2t

1

ns

RxFRAME High Pulse Width; CR10 = 1

t

24

–10

ns min

RxDATA Valid After RxCLK Rising Edge

10

ns max

t

25

10t

1

ns min

DxCLK Rising Edge to Last Falling Edge RxCLK

64t

1

ns max