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AD7013ARS 数据表(PDF) 2 Page - Analog Devices

部件名 AD7013ARS
功能描述  CMOS TIA IS-54 Baseband Receive Port
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7013ARS 数据表(HTML) 2 Page - Analog Devices

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Parameter
AD7013A
Units
Test Conditions/Comments
RECEIVE SECTION
ADC SPECIFICATION
Number of Input Channels
4
(IRx–IRx) and
QRx–QRx); CR12 = 0
(AUX IRx–AUX IRx) and
(AUX QRx–AUX QRx); CR12 = 1
Number of ADC Channels
2
Resolution
15
Bits
ADC Signal Range
2.6
Volts p-p
Measured Using an Input Sine Wave of 3 kHz
Differential Signal Range
V
BIAS ± 0.65
Volts
For Both Noninverting and
Inverting Analog Inputs
Single-Ended Signal Range
V
BIAS ± 1.3
Volts
For Noninverting Analog Inputs;
Inverting Analog Inputs = V
BIAS
V
BIAS
0.65 to (V
AA–0.65)
Volts min/max
Differential
1.3 to (V
AA–1.3)
Volts min/max
Single-Ended
Input Range Accuracy
±7.5
%
Accuracy
Bias Offset Error
±7.5
mV
Autocalibration; V
BIAS = min/max
±55
mV
User Calibration; I & Q Offset
Adjust Registers Equal to Zero
Dynamic Specifications
CMRR
–40
dB typ
Measured Using an Input Sine Wave of
3 kHz with Both Noninverting and
Inverting Inputs Tied Together
Dynamic Range
70
dB typ
Digital Mode Filter; CR11 = 0
65
dB typ
Analog Mode Filter; CR11 = 1
SNR2
65
dB min
Digital Mode Filter; CR11 = 0
68
dB typ
60
dB min
Analog Mode Filter; CR11 = 1
63
dB typ
Input Sampling Rate
1.5552/1.28
MHz
MCLK = 6.2208 MHz/5.12 MHz; MCLK/4
Output Word Rate
97.2/80
kHz
MCLK = 6.2208 MHz/5.12 MHz;
4
× Sampling of the Symbol Rate, MCLK/64
48.6/40
kHz
MCLK = 6.2208 MHz/5.12 MHz;
2
× Sampling of the Symbol Rate, MCLK/128
RECEIVE DIGITAL FILTERS
Digital Mode
MCLK = 6.2208 MHz
Root-Raised-Cosine
α = 0.35
Settling Time
329.2
µs
Absolute Group Delay
164.6
µs
Frequency Response
0–7.8975 kHz
±0.05
dB max
11.9 kHz
–3.0
dB
16.4025 kHz
–19
dB
> 30 kHz
–66
dB max
Analog Mode
MCLK = 5.12 MHz
Brick Wall Filter
Settling Time
400
µs
Absolute Group Delay
200
µs
Frequency Response
0–8 kHz
0 to –0.5
dB max
11.4 kHz
–3.0
dB
15 kHz
–24
dB
>17 kHz
–68
dB max
TIA IS-54 RECEIVE SPECIFICATIONS
Error Vector Magnitude3
2
% rms typ
Measured Using a Full-Scale Input
Error Offset Magnitude3
1
% rms typ
(V
AA = VDD = +5 V ± 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz;
T
A = TMIN to TMAX, unless otherwise noted)
–2–
REV. A
AD7013–SPECIFICATIONS1



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