REV. 0

AD7482

–5–

PIN FUNCTION DESCRIPTIONS

Pin

Number

Mnemonic

Description

1, 5, 13, 46

Positive Power Supply for Analog Circuitry

Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin

and AGND.

3, 4, 6, 11, 12,

AGND

Power Supply Ground for Analog Circuitry

14, 15, 47, 48

7VIN

Analog Input. Single-ended analog input channel.

8

REFOUT

Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF

capacitor must be placed between this pin and AGND.

9

REFIN

Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an

external voltage reference source, the reference voltage should be applied to this pin.

10

REFSEL

Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected

from this pin to AGND. When using an external reference source, this pin should be connected

directly to AGND.

16

STBY

Standby Logic Input. When this pin is logic high, the device will be placed in Standby Mode.

See Power Saving section for further details.

17

NAP

NAP Logic Input. When this pin is logic high, the device will be placed in a very low power mode.

See Power Saving section for further details.

18

CS

Chip Select Logic Input. This pin is used in conjunction with

RD to access the conversion result.

The databus is brought out of three-state and the current contents of the output register driven

onto the data lines following the falling edge of both

CS and RD. CS is also used in conjunction

with WRITE to perform a write to the offset register.

CS can be hardwired permanently low.

19

RD

Read Logic Input. Used in conjunction with

CS to access the conversion result.

20

WRITE

Write Logic Input. Used in conjunction with

CS to write data to the offset register. When the

desired offset word has been placed on the databus, the WRITE line should be pulsed high. It is

the falling edge of this pulse that latches the word into the offset register.

21

BUSY

Busy Logic Output. This pin indicates the status of the conversion process. The

BUSY signal goes

low after the falling edge of

CONVST and stays low for the duration of the conversion. In Parallel

Mode 1, the

BUSY signal returns high when the conversion result has been latched into the output

register. In Parallel Mode 2, the

BUSY signal returns high as soon as the conversion has been

completed, but the conversion result does not get latched into the output register until the falling

edge of the next

CONVST pulse.

22, 23

R1, R2

These pins should be pulled to ground via 100 k

Ω resistors.

24–28, 33–39

D0–D11

Data I/O Bits (D11 is MSB). These are three-state pins that are controlled by

CS, RD, and

29

Positive Power Supply for Digital Circuitry

30, 31

DGND

Ground Reference for Digital Circuitry

32

Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage the

interface logic of the device will operate.

40

D12

Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to

DGND via a 100 k

Ω resistor.

41

CONVST

Convert Start Logic Input. A conversion is initiated on the falling edge of the

CONVST signal.

The input track-and-hold amplifier goes from track mode to hold mode and the conversion process

commences.

42

RESET

Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a

conversion that may be in progress. The contents of the offset register will also be cleared on this

edge. Holding this pin low keeps the part in a reset state.

43

MODE2

Operating Mode Logic Input. See Table III for details.

44

MODE1

Operating Mode Logic Input. See Table III for details.

45

CLIP

Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that

is greater than positive full scale or less than negative full scale will be clipped to all “1s” or all “0s,”

respectively. Further details are given in the Offset/Overrange section.