REV. 0

AD7482

–11–

OFFSET/OVERRANGE

The AD7482 provides a

±8% overrange capability as well as a

programmable offset register. The overrange capability is achieved

by the use of a 13th bit (D12) and the CLIP input. If the CLIP

input is at logic high and the contents of the offset register are

zero, then the AD7482 operates as a normal 12-bit ADC. If the

input voltage is greater than the full-scale voltage, the data output

from the ADC will be all “1s.” Similarly, if the input voltage is

lower than the zero-scale voltage, the data output from the ADC

will be all “0s.” In this case, D12 acts as an overrange indicator. It

is set to “1” if the analog input voltage is outside the nominal 0 V

to 2.5 V range.

If the offset register contains any value other than “0,” the

contents of the register are added to the SAR result at the end

of conversion. This has the effect of shifting the transfer function

of the ADC as shown in Figure 11 and Figure 12. However,

it should be noted that with the CLIP input set to logic high,

the maximum and minimum codes that the AD7482 will output

will be 0xFFF and 0x000, respectively. Further details are given

in Table I and Table II.

Figure 11 shows the effect of writing a positive value to the offset

register. If, for example, the contents of the offset register

contained the value 256, then the value of the analog input

voltage for which the ADC would transition from reading all

“0s” to 000...001 (the bottom reference point) would be:

05

256

155 944

.

––

.

LSB

LSB

mV

The analog input voltage for which the ADC would read full-

scale (0xFFF) in this example would be:

25

15

256

2 3428

.

– .

–

.

V

LSB

LSB

V

ANALOG INPUT

0V

000...000

111...111

000...001

000...010

111...110

111...000

011...111

–OFFSET

Figure 11. Transfer Characteristic with Positive Offset

The effect of writing a negative value to the offset register is

shown in Figure 12. If a value of –128 was written to the offset

register, the bottom end reference point would now occur at:

05

128

78 43

.

––

.

LSB

LSB

mV

Following this, the analog input voltage needed to produce a

full-scale (0xFFF) result from the ADC would now be:

25

15

1282 5772

.

– .

––

.

V

LSB

LSB

V

000...000

0V

ANALOG INPUT

111...111

000...001

000...010

111...110

111...000

011...111

0.5LSB

–OFFSET

–OFFSET

Figure 12. Transfer Characteristic with Negative Offset

Table I shows the expected ADC result for a given analog input

voltage with different offset values and with CLIP tied to logic

high. The combined advantages of the offset and overrange

features of the AD7482 are shown clearly in Table II. It shows

the same range of analog input and offset values as Table I but

with the clipping feature disabled.

Table I. Clipping Enabled (CLIP = 1)

Offset

–128

0

+256

ADC DATA, D[0:11]

D12

–200 mV

0

0

0

1 1 1

–155.94 mV

0

0

0

1 1 0

0 V

0

0

256

1 0 0

+78.43 mV

0

128

384

0 0 0

+2.3428 V

3710

3838

4095

0 0 0

+2.5 V

3967

4095

4095

0 0 1

+2.5772 V

4095

4095

4095

0 1 1

+2.7 V

4095

4095

4095

1 1 1

Table II. Clipping Disabled (CLIP = 0)

Offset

–128

0

+256

ADC DATA, D[0:12]

–200 mV

–456

–328

–72

–155.94 mV

–384

–256

0

0 V

–128

0

256

+78.43 mV

0

128

384

+2.3428 V

3710

3838

4094

+2.5 V

3968

4096

4352

+2.5772 V

4095

4223

4479

+2.7 V

4552

4680

4936

Values from –327 to +327 may be written to the offset register.

These values correspond to an offset of

±200 mV. A write to the

offset register is performed by writing a 13-bit word to the part

as detailed in the Parallel Interface section. The 10 LSBs of the

13-bit word contain the offset value, while the 3 MSBs must

be set to “0.” Failure to write zeros to the 3 MSBs may result

in the incorrect operation of the device.