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AD7722AS 数据表(PDF) 4 Page - Analog Devices

部件名 AD7722AS
功能描述  16-Bit, 195 kSPS CMOS, Sigma-Delta ADC
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7722AS 数据表(HTML) 4 Page - Analog Devices

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AD7722
–4–
REV. 0
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Units
CLKIN Frequency
fCLK
0.3
12.5
15
MHz
CLKIN Period (tCLK = 1/fCLK)t1
0.067
0.08
3.33
µs
CLKIN Low Pulse Width
t2
0.45
× t
1
0.55
× t
1
CLKIN High Pulse Width
t3
0.45
× t
1
0.55
× t
1
CLKIN Rise Time
t4
5ns
CLKIN Fall Time
t5
5ns
FSI Low Time
t6
2tCLK
FSI Setup Time
t7
20
ns
FSI Hold Time
t8
20
ns
CLKIN to SCO Delay
t9
40
ns
SCO Period
1
t10
2tCLK
SCO Transition to FSO High Delay
t11
410
ns
SCO Transition to FSO Low Delay
t12
410
ns
SCO Transition to SDO Valid Delay
t13
38
ns
SCO Transition from FSI
2
t14
2.5
tCLK
SDO Enable Delay Time
t15
30
45
ns
SDO Disable Delay Time
t16
10
30
ns
DRDY
High Time
t17
2tCLK
Conversion Time1
t18
64
tCLK
DRDY
to CS Setup Time
t19
0ns
CS
to RD Setup Time
t20
0ns
RD
Pulse Width
t21
tCLK + 20
ns
Data Access Time after RD Falling Edge
3
t22
tCLK + 40
ns
Bus Relinquish Time after RD Rising Edge
t23
tCLK + 40
ns
CS
to RD Hold Time
t24
0ns
RD
to DRDY High Time
t25
1tCLK
SYNC/RESET Input Pulse Width
t26
10
ns
DVAL Low Delay from SYNC/RESET
t27
40
ns
SYNC/RESET Low Time Before CLKIN Rising
t28
10
ns
DRDY
High Delay after SYNC/RESET Low
t29
50
ns
DRDY
Low Delay after SYNC/RESET Low
1
t30
(8192 + 64)
tCLK
DVAL High Delay after SYNC/RESET Low
1
t31
8192
tCLK
CAL Setup Time
t34
10
ns
CAL Pulse Width
t35
12
tCLK
Calibration Delay from CAL High
t36
64
tCLK
Unipolar Input Calibration Time, (UNI = “0”)
1
t37
(3
× 8192 + 2 × 512)
tCLK
Bipolar Input Calibration Time, (UNI = “1”)1
t37
(4
× 8192 + 3 × 512)
tCLK
Conversion Results Valid, (UNI = “0”)
1
t38
(3
× 8192 + 2 × 512 + 64)
tCLK
Conversion Results Valid, (UNI = “1”)
1
t38
(4
× 8192 + 3 × 512 + 64)
tCLK
NOTES
1Guaranteed by design.
2Frame Sync is initiated on falling edge of CLKIN.
3With RD synchronous to CLKIN t
22, can be reduced up to 1 tCLK.
(AVDD= +5 V
5%, DVDD = +5 V
5%, AGND = DGND = 0 V, CL = 50 pF, TA = TMIN to TMAX,
fCLKIN = 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High)



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