AD7722

–19–

REV. 0

SERIAL INTERFACE

The AD7722’s serial data interface port allows easy interfacing

to industry standard digital signal processors. The AD7722

operates solely in the master mode providing three serial data

output pins for transfer of the conversion results. The serial data

clock output (SCO), serial data output (SDO) and frame sync

output (FSO) are all synchronous with CLKIN. SCO frequency

is always one-half the CLKIN frequency. FSO is continuously

output at the conversion rate of the ADC (FCLKIN/64). The

generalized timing diagrams in Figure 2 show how the AD7722

may be used to transmit its conversion results.

Serial data shifts out of the SDO pin synchronous with SCO.

The FSO is used to frame the output data transmission to an

external device. An output data transmission is 32 SCO cycles

in duration. The serial data shifts out of the SDO pin MSB first,

LSB last for a duration of 16 SCO cycles. For the next 16 SCO

cycles SDO outputs zeros.

Two control inputs, SFMT and CFMT, select the format for

the serial data transmission. FSO is either a pulse (approxi-

mately one SCO cycle in duration) or a square wave with a

period of 32 SCO cycles, depending on the state of the SFMT.

The logic level applied to SFMT also determines if the serial

data is valid on the rising or falling edge of the SCO. The clock

format pin, CFMT, simply switches the phase of SCO for the

selected FSO format.

With a logic low level on SFMT and CFMT set low (Figure 4),

FSO pulses high for one SCO cycle at the beginning of a data

transmission frame. When FSO goes low, the MSB is available

on the SDO pin after the rising edge of SCO and can be latched

on the SCO falling edge.

With a logic high level on SFMT and CFMT set low (Figure 4),

the data on the SDO pin is available after the falling edge of

SCO and can be latched on the SCO rising edge. FSO goes low

at the beginning of a data transmission frame when the MSB is

available and returns high after 16 SCO cycles.

The Frame Sync Input (FSI) can be used if the AD7722

conversion process must be synchronized to an external source.

FSI is an optional signal; if FSI is grounded or tied high frame,

syncs are internally generated. Frame sync allows the conver-

sion data presented to the serial interface to be a filtered and

decimated result derived from a known point in time. FSI can

be applied once after power-up, or it can be a periodic signal,

synchronous to CLKIN, occurring every 64 CLKIN cycles.

When FSI is applied for the first time, or if a low to high transition

is detected that is not synchronized to the output word rate, the

next 127 conversions should be considered invalid while the

digital filter accumulates new samples. Figure 4 shows how the

frame sync signal resets the serial output interface and how the

AD7722 will begin to output its serial data transmission frame.

A common frame sync signal can be applied to two or more

AD7722s to synchronize them to a common master clock.

Two Channel Multiplexed Operation

Three additional serial interface control pins (DOE, TSI and

CFMT) are provided. The connection diagram in Figure 39

shows how they are used to allow the serial data outputs of two

AD7722s to easily share one serial data line. Since a serial data

transmission frame lasts 32 SCO cycles, two AD7722s can share

a single data line by alternating transmission of their 16-bit

output data onto one SDO pin.

CFMT

SDO

SFMT

SCO

TSI

FSO

FSI

DOE

CLKIN

AD7722

MASTER

FSI

DOE

CLKIN

SDO

CFMT

SCO

SFMT

FSO

TSI

AD7722

SLAVE

DGND

FROM

CONTROL

LOGIC

TO HOST

PROCESSOR

Figure 39. Connection for Two Channel Multiplexed

Operation

The Data Output Enable pin (DOE) controls SDO’s output

buffer. When the logic level on DOE matches the state of the

TSI pin, the SDO output buffer drives the serial dataline;

otherwise the output of the buffer goes high impedance. The

serial format pin (SFMT) is set high to chose the frame sync

output format. The clock format pin (CFMT) is set high so that

CLKIN

FSI

SCO

FSO (MASTER)

FSI (SLAVE)

DOE (MASTER & SLAVE)

SDO (MASTER)

SDO (SLAVE)

D15

D14

D1

D0

D15

D14

D1

D0

Figure 40. Timing for Two Channel Multiplexed Operation