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AD7722AS 数据表(PDF) 6 Page - Analog Devices |
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AD7722AS 数据表(HTML) 6 Page - Analog Devices |
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6 / 24 page  AD7722 –6– REV. 0 t 15 t 16 DOE SDO Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low) t17 t20 t21 t 23 RD DB0 – DB15 t 22 VALID DATA t25 t24 t18 t19 CS DRDY Figure 6. Parallel Mode Read Timing CLKIN DVAL t30 t28 t26 t27 t31 t29 DRDY SYNC, RESET Figure 7. SYNC and RESET Timing, Serial and Parallel Mode CLKIN DVAL t36 t34 t35 t38 DRDY CAL t37 Figure 8. Calibration Timing, Serial and Parallel Mode |
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