WI.232FHSS-250-R datasheet(31/67 Pages) RADIOMETRIX

31 / 67 page

WI.232FHSS-25-R/ WI.232FHSS-250-R DATASHEET

Revision 1.1.0

Diagram courtesy of Silicon Laboratories Inc.

Figure 12: Wi.232FHSS Power-on and VDD Monitor Reset Time and Pin State

Parameter

Min

Typ

Max

Units

Notes

C2CK/RST Output Low Voltage

0.6

VDD = 2.7 – 3.6V

C2CK/RST Input Pull-up Current

μA

C2CK/RST = 0.0V

VDD Monitor Threshold (VRST)

2.40

2.55

2.70

Minimum C2CK/RST Low Time to

Generate a Hardware Reset

μs

Power-on Reset Delay (TPORDelay)

< 300

μs

VDD Ramp Time is Valid

Allowed/Valid VDD Ramp Time

Table 10, Wi.232FHSS Reset Circuit Specifications

3.6.6. Receive Signal Strength Indication (RSSI)

The RSSI pin contains an analog voltage proportional to the signal strength present on the channel at the

time. In normal operation, the module is hopping rapidly from channel to channel looking for valid data. In

this case, the RSSI value does not provide much in the way of useful information. However, it can be used to

keep a module awake. For instance, if you are preparing to put the module to sleep, you may sample the

RSSI pin to determine if it is processing a packet.

The Wi.232FHSS-250-R module has an internal, digital RSSI indication of ambient/immediate and of the last

good packet received. Additionally, with v1.1.0 and newer, the PROC_PKT pin can be used to indicate the

state of the packet engine.

RSSI level is dependent on the power of the signal received at the antenna port and the mode the LNA is in.

regLNAMODE controls the mode of the internal LNA, and has different values/meanings for the

WI.232FHSS-250-R 数据表(PDF) 31 Page - Radiometrix Ltd

WI.232FHSS-250-R 数据表(HTML) 31 Page - Radiometrix Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载