WI.232FHSS-250-R datasheet(12/67 Pages) RADIOMETRIX

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WI.232FHSS-25-R/ WI.232FHSS-250-R DATASHEET

Revision 1.1.0

Figure 3: Wi.232 Networking Concept

The module is designed to interface directly to a host UART. Three signals are used to transfer data

between the module and the host UART: TXD, RXD, and CTS. TXD is the data output from the module.

RXD is the data input to the module. CTS is an output that indicates the status of the module’s data

interface. If CTS is low, the module is ready to accept data. If CTS is high, the module is busy and the

host UART should not send any further data. The UART interface is capable of operating in full duplex at

baud rates from 2.4 to 115.2 kbps. The UART interface expects 1 start bit, 8 data bits (lsb first), and 1 stop

bit per byte with no parity (8-N-1).

Internally, the module has a 256 byte buffer for incoming characters from the host UART. The module can

be programmed to automatically transmit when the buffer reaches a programmed limit, set by

regUARTMTU. The module can also be programmed to transmit based on a delay between characters,

set by regTXTO (set in 1mSec increments). These registers allow the designer to optimize performance of

the module for fixed length and variable length data. The module supports streaming data, as well. To

optimize the module for streaming data, regUARTMTU should be set to 128. Additionally, regTXTO

should be set to a value greater than 1 UART byte time (10 bit times rounded up) at the current UART data

rate, or 2, whichever is greater. If the UART receive/RF transmit buffer becomes nearly full (about 224

bytes), the module will assert CTS high, indicating that the host should not send any more data. Data sent

by the host while CTS is high could be lost. When there is data in the UART receive/RF transmit buffer,

the BE pin is low; when this buffer is empty, BE is high.

When the MAC layer has a packet to send, it will optionally use a carrier-sense-multiple-access (CSMA)

protocol to determine if another module is already transmitting. If another module is transmitting, the

module will receive that data before attempting to transmit its data again. If, during this process, the UART

receive buffer gets full, the CTS line will go high to prevent the host UART from over-running the receive

buffer. The CSMA mechanism introduces a variable delay to the transmission channel. This delay is the

sum of a random period and a weighted period that is dependent on the number of times that the module

has tried and failed to acquire the channel. For applications that guarantee that only one module will be

transmitting at any given time, the CSMA mechanism can be turned off to avoid this delay.

WI.232FHSS-250-R 数据表(PDF) 12 Page - Radiometrix Ltd