AD775

REV. 0

–8–

AD817

1k

Ω

1k

Ω

5.6k

Ω

0V

DC

+5V

1.5V

DC

19

AD775

A

IN

1k

Ω

10

µF

Figure 13. Level Shifting Input Buffer

The analog input range is set by the voltage at the top and bot-

tom of the reference ladder. In general, the larger the span

converter; a 1.8 V span is suggested as a minimum to realize

good linearity performance. AS the input voltage exceeds 2.8 V

degrade the acquisition performance.

CLOCK INPUT

The AD775’s internal control circuitry makes use of both clock

edges to generate on-chip timing signals. To ensure proper

should be 25 ns or greater. For sampling frequencies at or near

20 MSPS, a 50% duty cycle clock is recommended. For slower

sampling applications, the AD775 can accommodate a wider

range of duty cycles, provided each clock phase is as least 25 ns.

Under certain conditions, the AD775 can be operated at sam-

pling rates above 20 MSPS. Figure 14 shows the signal-to-noise

plus distortion (S/(N+D)) performance of a typical AD775

versus clock frequency. It is extremely important to note that the

maximum clock rate will be a strong function of both temperature and

supply voltage. In general, the part slows down with increasing

temperature and decreasing supply voltage.

CLOCK FREQUENCY – MHz

50

40

0

0.1

1

100

10

30

20

10

Figure 14. S(N + D) vs. Clock Frequency (Temperature

= +25

°C)

A significant portion of the AD775’s power dissipation is pro-

portional to the clock frequency: Figure 15 illustrates this

tradeoff for a typical part.

CLOCK FREQUENCY – MHz

100

30

40

60

40

10

50

0

90

70

80

30

20

Figure 15. Power Dissipation vs. Clock Frequency

In applications sensitive to aperture jitter, the clock signal

should have a fall time of less than 3 ns. High speed CMOS

logic families (HC/HCT) are recommended for their symmetri-

cal swing and fast rise/fall times. Care should be taken to mini-

mize the fanout and capacitive loading of the clock input line.

DIGITAL INPUTS AND OUTPUTS

The AD775’s digital interface uses standard CMOS, with logic

The digital output is presented in straight binary format, with

loading of the digital output lines will increase the dynamic

power dissipation as well as the on-chip digital noise. Logic

fanout and parasitic capacitance on these lines should be mini-

mized for optimum noise performance.

The data output lines may be placed in a high output impedance

state by bringing OE (Pin 1) to a logic high. Figure 16 indicates

respectively). Note that even when the outputs are in a high

impedance state, activity on the digital bus can couple back to

the sensitive analog portions of the AD775 and corrupt conver-

sions in progress.

t

DD

t

HL

DATA ACTIVE

DATA

OUTPUT

OE

THREE-STATE

(HIGH IMPEDANCE)

t

t

Figure 16. High Impedance Output Timing