数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

AD7859LAS 数据表(PDF) 11 Page - Analog Devices

部件名 AD7859LAS
功能描述  3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCs
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7859LAS 数据表(HTML) 11 Page - Analog Devices

Back Button AD7859LAS Datasheet HTML 7Page - Analog Devices AD7859LAS Datasheet HTML 8Page - Analog Devices AD7859LAS Datasheet HTML 9Page - Analog Devices AD7859LAS Datasheet HTML 10Page - Analog Devices AD7859LAS Datasheet HTML 11Page - Analog Devices AD7859LAS Datasheet HTML 12Page - Analog Devices AD7859LAS Datasheet HTML 13Page - Analog Devices AD7859LAS Datasheet HTML 14Page - Analog Devices AD7859LAS Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 28 page
background image
AD7859/AD7859L
REV. A
–11–
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
START
Figure 4. Flowchart for Reading the Status Register
MSB
ZERO
ZERO
SGL/DIFF
CHSLT2
CHSLT1
CHSLT0
PMGT1
PMGT0
ONE
ONE
AMODE
BUSY
CALMD
CALSLT1
CALSLT0
STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit
Mnemonic
Comment
15
ZERO
These two bits are always 0.
14
ZERO
13
SGL/DIFF
Single/Differential Bit.
12
CHSLT2
Channel Selection Bits. These bits, in conjunction with the SGL/DIFF bit, determine which channel has
11
CHSLT1
been selected for conversion. Please refer to Table IIIa and Table IIIb.
10
CHSLT0
9
PMGT1
Power Management Bits. These bits along with the SLEEP pin indicate if the part is in a power-down
8
PMGT0
mode or not. See Table VI in Power-Down Section for description.
7
ONE
Both these bits are always 1.
6
ONE
5
AMODE
Analog Mode Bit. This bit is used along with SGL/DIFF and CHSLT2 – CHSLT0 to determine the
AIN(+) and AIN(–) inputs to the track and hold circuitry and the analog conversion mode (unipolar or bi-
polar). Please see Table III for details.
4
BUSY
Conversion/Calibration BUSY Bit. When this bit is a 1, there is a conversion or a calibration in progress.
When this bit is a zero, there is no conversion or calibration in progress.
3
CALMD
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a
system calibration is selected (see Table IV).
2
CALSLT1
Calibration Selection Bits. The CALSLT1 and CALSLT0 bits indicate which of the calibration
1
CALSLT0
registers are addressed for reading and writing (see section on the Calibration Registers for more details).
0
STCAL
Start Calibration Bit. The STCAL bit is a 1 if a calibration is in progress and a 0 if there is no calibration in
progress.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com